2002 Actel Legacy Product Information


	Legacy Product Information Datasheets \| Application Notes Product Brochures \| Software/Hardware Manuals

	Datasheets Accelerator Series FPGAs-ACT 3 Family Accelerator Series FPGAs-ACT 3 PCI Compliant Family ACT 1 Series FPGAs ACT 2 Series FPGAs Integrator Series FPGAs: 1200XL and 3200DX Families Package Characteristics and Mechanical Drawings Actel Hermetic Package Mechanical (Cavity, weight, lid size, and heat sink size) Configuration Application Notes 3200DX Dual-Port Random Access Memory (RAM) 3200DX Quadrant Clocks 3200DX Wide Decoding Modules A 155 Mbps ATM Network Interface Controller Using Actel's New 3200DX FPGAs A 256 Channel Control System Using FPGAs and a PLD A Power-on Reset (POR) Circuit for Actel Devices A Stepper Motor Controller in an Actel FPGA Design Files: app7.exe Board Level Considerations for Actel FPGAs Bus Translation Design Using FPGAs Designing FIR Filters with Actel FPGAs Design of an Active Noise Control System using Combinations of DSP and FPGAs Design of High Speed Communications Link using FPGAs Designing High Speed ATM Switch Fabrics by Using Actel FPGAs Design Files: app2.exe Designing State Machines for FPGAs Designing Telecommunication Applications Using Digital Signal Processing Functions with FPGAs Estimating Performance and Capacity of Actel Devices Fast On and Off Chip Delays with 1200XL and 3200DX I/O Latches Global Clock Networks in Actel Antifuse Devices HDL Methodology Offers Fast Design Cycle and Vendor Independence IBIS Models: Background and Usage Implementing Multipliers with Actel FPGAs Design Files: dt1.exe Implementing Three-state and Bidirectional Buses with Multiplexers in Actel FPGAs Introduction to Actel FPGA Architecture Metastability Characterization Report Metastability Characterization Report Errata Predicting Power Dissipation of Actel FPGAs RTL Register-based Memory Implementation Synchronous Dividers in Actel FPGAs Design Files: dt4.exe Three stating Actel Device I/O Pins for Board Level Testing Using ACT 3 Family I/O Macros Using BUFD and INVD Delay Macros Using FPGAs for 100 Mbit.sec Imagesetter Application Using FPGAs for Digital PLL Applications Using Silicon Explorer for System-level Debug Product Brochures Actel Products and Services Brochure Software and Hardware Manuals Silicon Explorer II User's Guide Silicon Sculptor User's Guide
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