Mobile
Verilog Online Help Prev Page Prev Page
Table of Contents
Bit-select
Block Statements
Built-in Primitives
Case Statement
Continuous Assignments
Conversion Functions
Comments
Compiler Directives
Concatenations
Conditional Operator
Delays
Disable Statement
Display Tasks
Edge Sensitive Path
Expression Bit Length
File I/O Functions
Functions
Identifiers
If Statement
Integer Constants
Intra-assignment Timing Controls
Keywords
Loop Statements
Memories
min:typ:max Delays
Module Declaration
Module Instantiation
Module Path Declaration
Module Path Polarity
Net Data Types
Operators
Parameters
Part-select
PLA Modeling Tasks
Probabilistic Distribution Functions
Procedural Assignments
Procedural Continuous Assignments
Procedural Timing Control
Range Specification
Real Constants
Register Data Types
Simulation Control Tasks
Simulation Time Functions
Specify Block
State Dependent Path
Stochastic Analysis Tasks
Strengths
Strings
Structured Procedures
Tasks
Timescale System Tasks
Timing Check Tasks
UDP Declaration
UDP Instantiation
UDP State Table
Value Change Dump (VCD) File
Vectors

Keywords

Formal Definition

Keywords are reserved identifiers, which are used to define language constructs.

List of keywords

always
and
assign
begin
buf
bufif0
bufif1
case
casex
casez
cmos
deassign
default
defparam
disable
edge
else
end
endcase
endfunction
endmodule
endprimitive
endspecify
endtable
endtask
event
for
force
forever
fork
function
highz0
highz1

if
initial
inout
input
integer
join
large
macromodule
medium
module
nand
negedge
nmos
nor
not
notif0
notif1
or
output
pmos
posedge
primitive
pull0
pull1
pulldown
pullup
rcmos
reg
release
repeat
rnmos
rpmos
rtran

rtranif0
rtranif1
scalared
small
specify
specparam
strong0
strong1
supply0
supply1
table
task
time
tran
tranif0
tranif1
tri
tri0
tri1
triand
trior
vectored
wait
wand
weak0
weak1
while
wire
wor
xnor
xor

 

Description

The keywords are reserved identifiers, which contain only lowercase letters. The user cannot redefine any of them.

 

Powered by IXwebhosting