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Formatting existing Verilog code
Printing Bold letters
 

Formatting existing Verilog code :by  Rajesh Bawankule
Many a times one need to work on a code which is poorly formatted. Here are some tips to make life easier.

Take a look at this poorly formatted code. Lets take this extreme example where code for flip-flop is written in just one line.

module flip_flop(clock, din, dout, set, reset); input clock, din, set, reset; output dout; reg    dout; always@(posedge clock or set or reset) begin if (!reset) dout <= 1'b0; else if (!set) dout <= 1'b1; else dout <= din; end endmodule // flip_flop

Verilog-XL provides a switch to see decompiled code. Run as
Verilog -d filename.v

In verilog.log file you will see this code. 

module flip_flop(clock, din, dout, set, reset);
    input
        clock,
        din,
        set,
        reset;
    output
        dout;
    reg
        dout;
    always
        @(posedge clock or set or reset)
            begin
                if(!reset)
                    dout <= #(0) 1'b0;
                else
                    if(!set)
                        dout <= #(0) 1'b1;
                    else
                        dout <= #(0) din;
            end
endmodule
// End of decompilation

Note that 
- This is tested only with Cadence Verilog-XL 2.6.38 and may not work with other simulators.
- All the user comments are lost.

I think in real life not many people face this extreme case. One definitely faces a code where though it is not in just one line but is poorly formatted. Take following case where there is no indentation.

module flip_flop(clock, din, dout, set, reset);
input clock,din,set,reset;
output dout;
reg dout;
always @(posedge clock or set or reset)
begin
if(!reset)
dout <= #(0) 1'b0;
else
if(!set)
dout <= #(0) 1'b1;
else
dout <= #(0) din;
end
endmodule

Use Emacs with Verilog mode installed. If you have not done so read the procedure at http://www.surefirev.com/verilog-mode.html

Open this file in Verilog mode. Select all the code and press MC\. This means Press  Meta_key, Control and \ keys simultaneously. And voila, code is now properly indented.

module flip_flop(clock, din, dout, set, reset);
   input clock,  din,  set,  reset;
   output dout;
   reg    dout;
   always @(posedge clock or set or reset)
     begin
 if(!reset)
   dout <= #(0) 1'b0;
 else
   if(!set)
     dout <= #(0) 1'b1;
   else
     dout <= #(0) din;
     end
endmodule



Printing Bold letters : by Rajesh Bawankule
Sometimes one need to print messages on screen with bold or inverted background to emphasis the importance. Following code snippet shows how to do it. 
Note that
- This is tested only with Cadence Verilog-XL 2.6.38 on UNIX and may not work with other simulators on other platforms.

module bold;

 initial begin

   $display ("Normal Text");
   $display ("\033[1mBold Text");
   $display ("\033[mSwitch back to Normal Text.....");
   $display ("\033[7mInverse Text.");
   $display ("\033[mSwitch back to Normal Text.....");

   $display ("\033[1mBold Text \033[mfollowed by \033[7mInverse text \033[m");
 end

endmodule
 

 

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