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RASSP Data Flow Graph Design Application Note

1.0 Executive Summary

Data flow representation of an algorithm is an effective technique for code development so that the algorithm may be executed in parallel on multiple signal processors. Usually, in signal processing applications, parallelization is required to meet a latency constraint. The issues involved in usage of the parallel constructs such as: Split and Merge, Mux and Demux, and Separate and Concatenate are all discussed in reference to the final autocoded result. The impact of additional issues associated with Data Flow graph primitive design and the impact upon the resultant code are then developed. The issues are: State, Memory management, construction and usage of the queues and static run schedules. These are the practical issues that affect the ability of the autocoding system to efficiently convert the graph to usable code. By properly designing the Data Flow graph data structure, the amount of processing and the size of the buffers (memory) required can be controlled. This paper presents guidelines for the usage of these concepts in the construction of the Data Flow graph. All the concepts will be illustrated by examples taken from the SAR and the ETC4ALFS on COTS Processors benchmark program applications. Case Studies on these two benchmarks programs are available by following the links provided.

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