EE481
COURSE POLICIES AND PROCEDURES
Fall 2003
Course Description
EE 481 is a digital design lab in which you will design and implement
digital
logic circuits. Experiments designing combinational and synchronous and
asynchronous sequential circuits will be conducted. There will be one
hour
of lecture and three hours of lab work per week. In lieu of students
buying a textbook you need to buy a parts kit
for the lab. The kit must contain large breadboard wire cutters, wire
strippers and standard 5v TTL ICs.
Computer Accounts
Computer accounts where you can access the WWW are required. These can
be Unix, Mac or Windows machines as long as they are on the net and
have
web browsing software. If you do not have access to any appropriate
machines
talk to the lab assistant in 510A CRMS. The Web page for the course is:
http://www.engr.uky.edu/~melham01/ee481/ee481.html.
Experiments
Students are encouraged to discuss the experiments with one another,
however,
students must submit only original work. Everything submitted for
grading
in this course with your name on it must be 100% original work. If any
portion of submitted material is not original work, UK policy dictates
that a failing grade for the course be assigned for all students
involved.
Failing the course is only the minimum penalty for more further details
see the Students Rights and Responsibilities. If you are
unclear
on this policy please see me.
Lab Write-ups
For each experiment done in this course you will prepare a write-up
describing
your pre-lab preparations and all work done in the lab.
For each lab, three things will be graded:
- pre-lab write-up (answers to pre-lab questions and your design)
- lab quiz (taken in lab)
- final lab write-up including TA signature sheet.
The pre-lab will consist of the following:
- Name, experiment number/title, and the date
- Answers to the pre-lab questions
- Timing diagrams, truth tables, etc. that were used in the
design
- Gate level logic diagram AND chip level wiring
diagram
for
your design
The pre-labs will be collected at the beginning of the lab section and
the quiz will be given. It is important that you be in lab on time or
you
will not have enough time to finish the quiz.
After the quiz the TA will chose one team to discuss their design
with
the class. This will offer you a chance to compare design alternatives
and benefits of alternate designs. If your design differs substantially
from the one presented describe the differences to the rest of the
class.
Each group will then work independently on their own circuit. The TA
will
check the operation of your circuit, verify that it meets the assigned
functionality, and sign your verification sheet.
The final report for the lab is due at the start of the next lab
meeting. NO LATE LAB REPORTS OR LATE PRE-LABS WILL BE ACCEPTED.
The final write-up will consist of the following:
- A brief summary of the experiment
- A description of any deviations from the pre-lab and the
reasons
for the change
- Tables or figures with any measurements taken during the
experiment
and a discussion of the results
- A description of the final result (did it work, how well,
why,
why
not) and a discussion of the optimality of your design (if your design
was not optimal in chip/gate counts etc. why not)
- The signature sheet
Practical Exams & Project
There will be two semester lab practical exams but no final exam.
Unless changed explicitly in lecture, the practical will be scheduled
as
follows:
Practical 1: the week of Oct. 6, '03 in lab.
Practical 2: the week of Nov. 10, '03 in lab.
The format and content of the practical and exam will be discussed
in
class prior to each. There will not be a final exam in EE481 but
instead
there will be one hardware project due before finals week of
class.
The project and write up will
count 10% toward your final grade. For successful completion of
the project requires thorough understanding of previous labs.
Makeup Exams/Practicals
For those students who have verified conflicts, makeup exams
will
be arranged on an individual basis. In order to obtain approval for a
conflict
known ahead of time you must inform the instructor at least one week
before
the scheduled exam date. Verified conflicts are defined in the Students
Rights and Responsibilities.
Extra Credit
No extra credit projects will be assigned or graded.
Grades
The raw percentage in the course will be based on the following
weights:
| Experiments & Write-ups |
25% |
| Project & Write-up |
10% |
| Pre-Labs |
10% |
| Quizzes |
15% |
| Practical #1 |
20% |
| Practical #2 |
20% |
Re-grades
Re-grades incur a considerable amount of administrative overhead. In
addition,
they are unfair to the majority of students who accept the grade they
receive.
All assignments will be graded fairly, uniformly, and with great care.
The students are expected to respect the judgment of the teaching
assistants
in evaluating graded assignments. However, students should not be
unfairly
penalized by ``human error,'' such as errors in totaling up scores on
an
exam questions. Therefore, the re-grade policy for this class is as
follows.
To submit graded material for re-grade, describe the mistake on a
separate
sheet of paper and attach the sheet to the exam or homework. The
re-grade
request must be submitted to the Prof. (not the TA) by noon the day
after
the exam or homework is returned. Furthermore, the request for re-grade
will make the entire assignment open for re-grade, that is, ALL
of the grading on a particular exam or homework in question can be
checked
for fairness and accuracy.
The final grade will be determined largely based upon if you have
completed the projects and turned in the prelabs and postlabs. As long
as you are doing the work, turning in the pre-lab and post-lab and
finishing the lab on time you should have little problem recieving a
good grade. However the following penalties will be applied if you do
not complete the following types of work on time.
No prelab - minus 1/3 letter grade.
No postlab - minus 1/3 letter grade.
No schematic before class - minus 1/4 letter grade.
Not showing up for a quiz - minus 1/4 letter grade.
Not finishing a lab by the start of the next lab - minus 1/4
letter grade.
Not finishing a lab by the end of the semester - minus 1/4
additional letter grade.
Course Goals and
Outcomes
1. Ability to synthesize and analyze combinatorial digital logic
circuits using discrete logic circuits, proms, encoders/decoders and
programmable array logic (PALs).
2. Ability to synthesize and analyze sequential digital logic
circuits using discrete logic circuits, proms, encoders/decoders and
programmable array logic (PALs).
3. Ability to read and understand technical specifications and
apply to current design.
4. Ability to formulate engineering problem and to solve them using
a top-down approach.
Mike Lhamon
Aug. 27, 2003
Course
Syllabus