// 
// SYNTHETIC PIC 2.0                                          4/23/98
//
//    This is a synthesizable Microchip 16C57 compatible
//    microcontroller.  This core is not intended as a high fidelity model of
//    the PIC, but simply a way to offer a simple processor core to people
//    familiar with the PIC who also have PIC tools.  
//
//    pictest.v  -   top-level testbench (NOT SYNTHESIZABLE)
//    piccpu.v   -   top-level synthesizable module
//    picregs.v  -   register file instantiated under piccpu
//    picalu.v   -   ALU instantiated under piccpu
//    picidec.v  -   Instruction Decoder instantiated under piccpu
//    hex2rom.c  -   C program used to translate MPLAB's INTEL HEX output
//                   into the Verilog $readmemh compatible file
//    test*.asm  -   (note the wildcard..) Several test programs used
//                   to help debug the verilog.  I used MPLAB and the simulator
//                   to develop these programs and get the expected results.
//                   Then, I ran them on Verilog-XL where they appeared to
//                   match.
//
//    Copyright, Tom Coonan, '97.
//    Use freely, but not for resale as is.  You may use this in your
//    own projects as desired.  Just don't try to sell it as is!
//
//

// This is an expansion module used as an example for how to add
// new circuitry to the core.  All expansion modules should use
// the expansion bus as shown in this example.  This module does
// nothing very interesting in itself.  The test program 'test10.asm'
// is the test program that exercises this module.
//
// Let's see.  Maintain an 'x' register.  If PIC core reads it, then
// autoincrement it.  Allow PIC to write it.
//
// Address  Direction   Description
//   7E       R           Offer x, which is an autoincremented
//   7F       W           Set x
//    
//
module picexp1 (
   clk,
   reset,

   expdin,
   expdout,
   expaddr,
   expread,
   expwrite
);

input		clk;
input		reset;

// Expansion Interface
output [7:0]	expdin;		// TO the PIC core.
input [7:0]	expdout;	// FROM the PIC core.
input [6:0]	expaddr;	// Address
input		expread;	// Asserted (high) when PIC is reading FROM us.
input		expwrite;	// Asserted (high) when PIC is writing TO us.

reg [7:0]	expdin;

// An internal register is this expansion module.
reg [7:0]	x;

// Drive the expdin bus back to the PIC.  This should just be a MUX.
// For several different expansion submodules, this would be our gateway
// MUX back to the PIC core.
//
always @(expread or expaddr) begin
   if (expread & (expaddr == 7'h7E)) begin
      expdin <= x;
   end
   else begin
      // Drive output to FF just to indicate we don't see a read right now.
      expdin <= 8'hFF;
   end
end

// synopsis translate_off
always @(posedge clk) begin
   #5;
   if (expread & (expaddr == 7'h7E)) begin
      $display ("PICEXP1:  The PIC is reading from the expansion circuit, providing %0h", x);
   end
end
// synopsis translate_on

// Implement the x register
//
always @(posedge clk) begin
   if (reset) begin
      x <= 8'h00;
   end
   else begin
      if (expread & (expaddr == 7'h7E)) begin
         x = x + 1;
      end
      else if (expwrite & (expaddr == 7'h7F)) begin
         $display ("PICEXP1:  The PIC has written to the expansion circuit, %0h", expdout);
         x <= expdout;
      end
   end
end
endmodule