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The network architecture specifies the topology of the network, as well as the bandwidth and protocol requirements for the individual network
links. Typical network topology families for digital processing systems include: bus, ring, mesh, cube, tree, and custom configurations.
Topologies are selected to match the particular data transfer patterns of the specific application. Performance simulations provide information
concerning link and processor utilization measurements for specific topology, processor element (PE) type and software mapping
combinations.
The software-to-hardware mapping divides the application algorithm into separate tasks, which are allocated to the individual PEs. The tasks are
then scheduled according to their relative data dependencies and the overall processing latency constraints. Various combinations of mapping
and scheduling methods can be tested and selected. For example, depending on the application, the mapping and scheduling can be assigned at
design-time (i.e. statically) or at run-time (i.e. dynamically).
There is no efficient, general, closed-form, optimum solution to the partitioning, mapping, and scheduling problem. It is an
not-polynomial-(NP)-complete problem. Consequently, many iterative, heuristic, and manual techniques are currently applied. The
performance models facilitate these methods, as shown in figure 2 - 1.
Subject to the following goals:
The information above is the information that the performance modeling design activity is based upon and uses as input to the process.
An architecture is the combination of processing element types as distinguished by their unique processing rates, memory sizes and locations, and network configuration, bandwidth, and protocol types. There are many potential architectural combinations, and there are many permutations for mapping the application algorithm onto each architecture. The performance model helps the designer understand the impact of architectural/mapping decisions and helps develop strategies for quickly arriving at an optimal solution. The following output from performance models guides the development process:
When the designer selects the final architecture and mapping, the performance model will have validated the solution in
terms of its overall processing throughput and latency.
2.0 Purposes
The primary purposes of a token-based performance model are to determine the sizes, architecture, software-to-hardware mapping, and
performance requirements for each of the major components of the system. Specifically, it determines the sufficiency of the following selections
in meeting the system processing throughput and latency requirements:
The total processing latency, throughput, and physical constraints on the processing system drive the optimization of the processing architecture
in terms of the number and type of processing elements, and the memory and buffer requirements.
2.1 Starting Information
Upon initiating performance modeling activities within the architecture design process, the designer bases selections on the following requirement information that is derived from the system design process:
2.2 Results Information
Token-based Performance Modeling is conducted to support the Architecture Design process. The goal of the Architecture Design process is to select an architecture that best satisfies the criteria of section 2.1 above. In this role, the performance
model is used to evaluate architecture candidates to determine the :
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