Next: Up: Appnotes Index Previous:8.0 Specifications
Next:
Up: Appnotes Index
Previous:8.0 Specifications
RASSP Methodology Document, Version 2.0, Volume I, Lockheed Martin Advanced Technology Laboratories, October, 1995. [METHODOLOGY_95]
[PGM] Processing Graph Method Specification: Version 1.0, Navy Standard Signal
Processing Program. (PMS-500), December 1987
[To obtain these documents and other information regarding PGM refer to the PGMT home page presented by the Processing System Section, Advanced Information Technology Branch at the Naval Research Laboratory, Washington, D.C. www.ait.nrl.navy.mil/pgmt/pgm2.html or contact Mr. David Laplan at phone number (202) 404-7338 or e-mail kaplar@ait.nrl.navy.mil ]
"VSIA Alliance Architecture Document Version 1.0," Virtual Socket Interface Alliance, http://www.vsi.org/library//vsi-or.pdf, 1997.
Standard Virtual Interface
Buchanan, G., "Hardware Synthesis Study of WSSPT SVI Interface Encapsulations," Lockheed Martin Advanced Technology Laboratories, July, 1995. [PCI_SVI]
Reconfigurable Network Interface
Buchanan, G., "Myrinet to SVI External Network Interface," Lockheed Martin Advanced Technology Laboratories, July 31, 1996. [Myri_SVI]
Wedgwood, J., "Reconfigurable Network Interface (RNI) Study: Myrinet to PCI," Lockheed Martin Advanced Technology Laboratories, August, 1997. [Myri_PCI]
Buchanan, G., "SVI Verification Task, Case 2 - RNI Encapsulation Study VHDL Model Description (Simple RNI) -Encapsulation Study Using the Cypress HOTLink high-speed serial link and the PCI fabric interface to implement a sensor-to-PCI RNI," Lockheed Martin Advanced Technology Laboratories, Sept. 20, 1995. [Hotlink_PCI]
9.0 References
9.1 Documents
Chhabra, A., "SVI Verification Study: Encapsulations of the Benchmark II-Data I/O Board and the Mercury Rino-RIC Chipset," Lockheed Martin Advanced Technology Laboratories, May 17, 1996. [Data_IO_RINO]
Buchanan, G., "RACEway to SVI External Network," Lockheed Martin Advanced Technology Laboratories, July 30, 1996. [RACE_SVI]
9.2 Papers
Wedgwood, J., and G. Buchanan, "A Model-Year Architecture Approach to Hardware Reuse in Digital Signal Processor System Design," Proceedings High-Level Electronic System Design Conference, San Jose, CA, October, 1997, pp 493 - 504. [Wedgwood_97]
9.3 Application Notes
Methodology
Hardware/Software Codesign
Design for Test
Data Flow Graph Design
Terminology and Taxonomy
Token-Based Performance Modeling
Autocoding for DSP Control
9.4 Case Studies
Synhetic Aperture Radar [SAR-CS]
ETC4ALFS on COTS Processor [UYS-CS]
Semi-Automated Image intelligence Processor [SAIP-CS]
Next:
Up: Appnotes Index
Previous:8.0 Specifications