library ieee;
use ieee.std_logic_1164.all;
use std.textio.all;
use ieee.std_logic_arith.all;

use work.txt_util.all;
 
 
entity TLOOP is
end TLOOP; 


architecture test of TLOOP is

constant tSU_R: time := 5 ns;
constant tSU_W: time := 6 ns; 
 
signal W:   std_logic;
signal R:   std_logic;
signal RST: std_logic;

begin

RST <= '0', '1' after 12 ns, '0' after 20 ns;

-- verify the setup time on W and R signals
-- we assume W and R are asserted alternatingly

timing_check: process

variable w_asserted: time;
variable r_asserted: time;

begin

-- wait for DUT to be reset
wait until RST = '1';
wait until RST = '0';
  
 loop
    wait until W = '0';
    w_asserted := now;
    wait until W = '1';

    print("I@TB: detected W access");

    assert (now - w_asserted) >= tSU_W
      report "E@TB: W setup time too short"
      severity Error;
      
      
    -- verify read access                      
    wait until R = '0';
    r_asserted := now;
    wait until R = '1';  

    print("I@TB: detected R access");

    assert (now - r_asserted) >= tSU_R
      report "E@TB: R setup time too short"
      severity Error;
	  
 end loop;

end process timing_check;


-- description of the timing behaviour
-- of the DUT implemenation            
dut: process

begin

W <= '1';
R <= '1';

wait until RST = '1';
wait until RST = '0';

wait for 10 ns;

-- write access
W <= '0', '1' after 8 ns;
wait for 10 ns;

-- read access
R <= '0', '1' after 9 ns;
wait for 10 ns;

-- write access
W <= '0', '1' after 7 ns;
wait for 10 ns;

-- read access
R <= '0', '1' after 4 ns; -- this is a violation we want to detect
wait for 10 ns;

-- write access
W <= '0', '1' after 8 ns;
wait for 10 ns;

wait;


end process dut;                    
                    
              
              
end test;