library ieee;
use ieee.std_logic_1164.all;
use std.textio.all;
use ieee.std_logic_arith.all;

use work.txt_util.all;
 
 
entity TB1 is
end TB1; 


architecture test of TB1 is


signal x1:    std_logic;
signal x2:    std_logic;
signal y:     std_logic;

begin


test_seq: process

variable cnt: integer := 0;
--*variable slv: std_logic_vector(X2'range);

begin
  
x1 <= '0';
x2 <= '0';

wait for 10 ns;

x1 <= '1';
x2 <= '0';

wait for 10 ns;
     
x1 <= '0';
x2 <= '1';
                 
                 
wait for 10 ns;

x1 <= '1';
x2 <= '1';
  
wait for 10 ns;

assert y = (x1 xor x2)
  report "E@TB: circuit failed"
  severity Error;

assert y = (x1 xor x2)
  report "E@TB: failure at: x1="& std_logic'image(x1)&
         " x2="& std_logic'image(x2)
  severity Error;
  
assert y = (x1 xor x2)
  report "E@TB: failure at: x1="& str(x1)& " x2="& str(x2)
  severity Error;
  
  
  

x1 <= 'X';
x2 <= 'X';

wait for 30 ns;

x1 <= '1', '0' after 10 ns, '1' after 20 ns, '0' after 30 ns;
x2 <= '1', '0' after 20 ns;


wait; -- stop process


end process test_seq;


-- this is supposed to be an xor ... but it isn't
y <= (x1 and not x2) or (x2 and not x1) or (x1 and x2);

              
end test;