library ieee;
use ieee.std_logic_1164.all;
use std.textio.all;
use ieee.std_logic_arith.all;

use work.txt_util.all;
 
 
entity SIMPLE_MON is
end SIMPLE_MON; 


architecture test of SIMPLE_MON is

signal INT_L: std_logic;

begin

-- example stimulus
INT_L <= '1', '0' after 30 ns, '1' after 200 ns;



-- report changes of the interrupt signal

monitor: process(INT_L)

begin
  
  print("I@TB: INT_L="& str(INT_L));
  
end process monitor;


-- report when interrupt is asserted                      
print(INT_L'event and INT_L = '0', "I@TB: INT_L="& str(INT_L)); 
              
              
end test;