Answers to Delay Exercises
The transition bounds for the sum output are 3
and 6 for a rising output, and also 2 and
5 for a falling output.
The total delay before the carry_out of
the 4-bit ripple carry adder can be guaranteed to be safe is 36.
For the 4-bit ripple carry adder, the worst case input vectors are :
a = 4'b1111; b = 4'b0000; carry_in = 1;
Or :
a = 4'b0000; b = 4'b1111; carry_in = 1;
Normally the carry_in inputs are set to zero prior to each
addition. When a carry skips a block that is propagating its
carry_in, that block will eventually output the
carry signal - it just takes longer to do so. Since these
two signals are OR'ed together to form the
carry_in input to the next block, it doesn't actually matter
that the propagated carry takes such a long time to reach the
next block - the carry_in has already been set by the
carry that skipped the block. This is the advantage of the
carry skip.
However, if the carry_in nodes are not set to zero at the
beginning of each addition, but left holding the value they last had, the
following situation may arise : if the previous block doesn't generate or
propagate a carry (i.e. its carry_out is 0), the
current block had previously been outputting a 1 on
its carry_out and is now propagating its
carry_in, then although the 0 input will skip
around the current block up to the OR gate, the old
carry_out will keep the OR gate switched on.
The gate will not correctly switch off until the new carry_in
propagates all the way through the block. This means that the carry skip
is ineffective under these circumstances, and may even lead to the wrong
answer being generated, as the wrong carry_in may be
propagated further up the chain, and may not be corrected before the
output is latched to the next part of the circuit.
Replacing the OR gate and the immediately preceding
AND gate by a single 2-1, 1-bit multiplexor controlled by the
block's propagate signal will solve the problem, as it will
switch a zero carry_in straight through as soon as the
control signal changes. (Note : There are many other viable
solutions, but this is one of the simplest.)
The output from the various modules is :
blocking
0 : a = 2 b = 5 c = 1 d = 1 e = 2
1 : a = 1 b = 5 c = 1 d = 1 e = 2
2 : a = 3 b = 5 c = 0 d = 3 e = 1
4 : a = 4 b = 5 c = 0 d = 3 e = 1
6 : a = 7 b = 6 c = 0 d = 3 e = 1
c, d, e - done
7 : a = 7 b = 6 c = 7 d = 2 e = 1
a, b - done
8 : a = 2 b = 6 c = 7 d = 2 e = 1
non_blocking
0 : a = 2 b = 5 c = 1 d = x e = x
1 : a = 1 b = 5 c = 1 d = x e = x
2 : a = x b = 5 c = 0 d = 3 e = x
4 : a = 4 b = 5 c = 0 d = 3 e = x
6 : a = 7 b = 6 c = 0 d = 3 e = x
c, d, e - done
7 : a = 7 b = 6 c = 7 d = 2 e = x
a, b - done
8 : a = 2 b = 6 c = 7 d = 2 e = x
blocking_intra
0 : a = 2 b = 5 c = 1 d = 1 e = 2
1 : a = x b = 5 c = 1 d = 1 e = 2
2 : a = 1 b = 5 c = 0 d = 3 e = 1
4 : a = 4 b = 5 c = 0 d = 3 e = 1
6 : a = 7 b = 6 c = 0 d = 3 e = 1
c, d, e - done
7 : a = 7 b = 6 c = x d = 2 e = 1
a, b - done
8 : a = 3 b = 6 c = x d = 2 e = 1
non_blocking_intra
a, b - done
c, d, e - done
0 : a = 2 b = 6 c = 0 d = 2 e = x
1 : a = x b = 6 c = 0 d = 2 e = x
5 : a = x b = 6 c = x d = 2 e = x
With the clock period cut to 10, lots of setup violations occur in some of
the flip-flops of the rungs of the move generator tower.
With the clock period set to 15, there are no longer any setup violations,
but some of the outputs are shown as either z, x
or X. This is due to the propagation delay through some of
the elements of the bit-sliced move generators being longer than the clock
period.
The maximum clock frequency is calculated by first finding the minimum
clock period at which the circuit functions correctly. This turns out to
be 19 time steps. Since each timestep represents 10 ns (from the
`timescale directive at the start of the file), this means
that the minimum clock period is 190 ns. The maximum clock frequency is
the reciprocal of this (1 / 0.000000190) = 5263157.9 Hz, or approximately
5.25 MHz.
Using the negative edge of the clock to latch some of the signals does not
usually alter the critical path through a particular part of a circuit.
Thus, in using the negative edge of the clock, as well as the
positive edge, the clock period cannot be reduced and may be increased
since both phases must be greater than the maximum delay of their
respective portions of the critical path.
Last modified: Mon Oct 27 11:46:00 GMT 1997
by Gerard M. Blair