Warning: verify failed: 'intf_mode == VK_BadMode || 		intf_mode == VK_InternalMode || 		intf_mode == VK_InMode || 		intf_mode == VK_InoutMode || 		intf_mode == VK_OutMode || 		intf_mode == VK_BufferMode || 		intf_mode == VK_LinkageMode'

Warning: verify failed: 'intf_mode == VK_BadMode || 		intf_mode == VK_InternalMode || 		intf_mode == VK_InMode || 		intf_mode == VK_InoutMode || 		intf_mode == VK_OutMode || 		intf_mode == VK_BufferMode || 		intf_mode == VK_LinkageMode'

Warning: verify failed: 'intf_mode == VK_BadMode || 		intf_mode == VK_InternalMode || 		intf_mode == VK_InMode || 		intf_mode == VK_InoutMode || 		intf_mode == VK_OutMode || 		intf_mode == VK_BufferMode || 		intf_mode == VK_LinkageMode'

Warning: verify failed: 'intf_mode == VK_BadMode || 		intf_mode == VK_InternalMode || 		intf_mode == VK_InMode || 		intf_mode == VK_InoutMode || 		intf_mode == VK_OutMode || 		intf_mode == VK_BufferMode || 		intf_mode == VK_LinkageMode'

Warning: verify failed: 'intf_mode == VK_BadMode || 		intf_mode == VK_InternalMode || 		intf_mode == VK_InMode || 		intf_mode == VK_InoutMode || 		intf_mode == VK_OutMode || 		intf_mode == VK_BufferMode || 		intf_mode == VK_LinkageMode'

Warning: verify failed: 'intf_mode == VK_BadMode || 		intf_mode == VK_InternalMode || 		intf_mode == VK_InMode || 		intf_mode == VK_InoutMode || 		intf_mode == VK_OutMode || 		intf_mode == VK_BufferMode || 		intf_mode == VK_LinkageMode'

Warning: verify failed: 'intf_mode == VK_BadMode || 		intf_mode == VK_InternalMode || 		intf_mode == VK_InMode || 		intf_mode == VK_InoutMode || 		intf_mode == VK_OutMode || 		intf_mode == VK_BufferMode || 		intf_mode == VK_LinkageMode'

Warning: verify failed: 'intf_mode == VK_BadMode || 		intf_mode == VK_InternalMode || 		intf_mode == VK_InMode || 		intf_mode == VK_InoutMode || 		intf_mode == VK_OutMode || 		intf_mode == VK_BufferMode || 		intf_mode == VK_LinkageMode'

Warning: verify failed: 'intf_mode == VK_BadMode || 		intf_mode == VK_InternalMode || 		intf_mode == VK_InMode || 		intf_mode == VK_InoutMode || 		intf_mode == VK_OutMode || 		intf_mode == VK_BufferMode || 		intf_mode == VK_LinkageMode'

Warning: verify failed: 'intf_mode == VK_BadMode || 		intf_mode == VK_InternalMode || 		intf_mode == VK_InMode || 		intf_mode == VK_InoutMode || 		intf_mode == VK_OutMode || 		intf_mode == VK_BufferMode || 		intf_mode == VK_LinkageMode'

Warning: verify failed: 'intf_mode == VK_BadMode || 		intf_mode == VK_InternalMode || 		intf_mode == VK_InMode || 		intf_mode == VK_InoutMode || 		intf_mode == VK_OutMode || 		intf_mode == VK_BufferMode || 		intf_mode == VK_LinkageMode'

Warning: verify failed: 'intf_mode == VK_BadMode || 		intf_mode == VK_InternalMode || 		intf_mode == VK_InMode || 		intf_mode == VK_InoutMode || 		intf_mode == VK_OutMode || 		intf_mode == VK_BufferMode || 		intf_mode == VK_LinkageMode'

Warning: verify failed: 'intf_mode == VK_BadMode || 		intf_mode == VK_InternalMode || 		intf_mode == VK_InMode || 		intf_mode == VK_InoutMode || 		intf_mode == VK_OutMode || 		intf_mode == VK_BufferMode || 		intf_mode == VK_LinkageMode'

Warning: verify failed: 'intf_mode == VK_BadMode || 		intf_mode == VK_InternalMode || 		intf_mode == VK_InMode || 		intf_mode == VK_InoutMode || 		intf_mode == VK_OutMode || 		intf_mode == VK_BufferMode || 		intf_mode == VK_LinkageMode'

Warning: verify failed: 'intf_mode == VK_BadMode || 		intf_mode == VK_InternalMode || 		intf_mode == VK_InMode || 		intf_mode == VK_InoutMode || 		intf_mode == VK_OutMode || 		intf_mode == VK_BufferMode || 		intf_mode == VK_LinkageMode'

Warning: verify failed: 'intf_mode == VK_BadMode || 		intf_mode == VK_InternalMode || 		intf_mode == VK_InMode || 		intf_mode == VK_InoutMode || 		intf_mode == VK_OutMode || 		intf_mode == VK_BufferMode || 		intf_mode == VK_LinkageMode'

Warning: verify failed: 'intf_mode == VK_BadMode || 		intf_mode == VK_InternalMode || 		intf_mode == VK_InMode || 		intf_mode == VK_InoutMode || 		intf_mode == VK_OutMode || 		intf_mode == VK_BufferMode || 		intf_mode == VK_LinkageMode'

Warning: verify failed: 'intf_mode == VK_BadMode || 		intf_mode == VK_InternalMode || 		intf_mode == VK_InMode || 		intf_mode == VK_InoutMode || 		intf_mode == VK_OutMode || 		intf_mode == VK_BufferMode || 		intf_mode == VK_LinkageMode'

Warning: verify failed: 'intf_mode == VK_BadMode || 		intf_mode == VK_InternalMode || 		intf_mode == VK_InMode || 		intf_mode == VK_InoutMode || 		intf_mode == VK_OutMode || 		intf_mode == VK_BufferMode || 		intf_mode == VK_LinkageMode'

Warning: verify failed: 'intf_mode == VK_BadMode || 		intf_mode == VK_InternalMode || 		intf_mode == VK_InMode || 		intf_mode == VK_InoutMode || 		intf_mode == VK_OutMode || 		intf_mode == VK_BufferMode || 		intf_mode == VK_LinkageMode'

Warning: verify failed: 'intf_mode == VK_BadMode || 		intf_mode == VK_InternalMode || 		intf_mode == VK_InMode || 		intf_mode == VK_InoutMode || 		intf_mode == VK_OutMode || 		intf_mode == VK_BufferMode || 		intf_mode == VK_LinkageMode'

Warning: verify failed: 'intf_mode == VK_BadMode || 		intf_mode == VK_InternalMode || 		intf_mode == VK_InMode || 		intf_mode == VK_InoutMode || 		intf_mode == VK_OutMode || 		intf_mode == VK_BufferMode || 		intf_mode == VK_LinkageMode'

Warning: verify failed: 'intf_mode == VK_BadMode || 		intf_mode == VK_InternalMode || 		intf_mode == VK_InMode || 		intf_mode == VK_InoutMode || 		intf_mode == VK_OutMode || 		intf_mode == VK_BufferMode || 		intf_mode == VK_LinkageMode'

Warning: verify failed: 'intf_mode == VK_BadMode || 		intf_mode == VK_InternalMode || 		intf_mode == VK_InMode || 		intf_mode == VK_InoutMode || 		intf_mode == VK_OutMode || 		intf_mode == VK_BufferMode || 		intf_mode == VK_LinkageMode'

Warning: verify failed: 'intf_mode == VK_BadMode || 		intf_mode == VK_InternalMode || 		intf_mode == VK_InMode || 		intf_mode == VK_InoutMode || 		intf_mode == VK_OutMode || 		intf_mode == VK_BufferMode || 		intf_mode == VK_LinkageMode'

Warning: verify failed: 'intf_mode == VK_BadMode || 		intf_mode == VK_InternalMode || 		intf_mode == VK_InMode || 		intf_mode == VK_InoutMode || 		intf_mode == VK_OutMode || 		intf_mode == VK_BufferMode || 		intf_mode == VK_LinkageMode'

Warning: verify failed: 'intf_mode == VK_BadMode || 		intf_mode == VK_InternalMode || 		intf_mode == VK_InMode || 		intf_mode == VK_InoutMode || 		intf_mode == VK_OutMode || 		intf_mode == VK_BufferMode || 		intf_mode == VK_LinkageMode'

Warning: verify failed: 'intf_mode == VK_BadMode || 		intf_mode == VK_InternalMode || 		intf_mode == VK_InMode || 		intf_mode == VK_InoutMode || 		intf_mode == VK_OutMode || 		intf_mode == VK_BufferMode || 		intf_mode == VK_LinkageMode'

Warning: verify failed: 'intf_mode == VK_BadMode || 		intf_mode == VK_InternalMode || 		intf_mode == VK_InMode || 		intf_mode == VK_InoutMode || 		intf_mode == VK_OutMode || 		intf_mode == VK_BufferMode || 		intf_mode == VK_LinkageMode'

Warning: verify failed: 'intf_mode == VK_BadMode || 		intf_mode == VK_InternalMode || 		intf_mode == VK_InMode || 		intf_mode == VK_InoutMode || 		intf_mode == VK_OutMode || 		intf_mode == VK_BufferMode || 		intf_mode == VK_LinkageMode'

Warning: verify failed: 'intf_mode == VK_BadMode || 		intf_mode == VK_InternalMode || 		intf_mode == VK_InMode || 		intf_mode == VK_InoutMode || 		intf_mode == VK_OutMode || 		intf_mode == VK_BufferMode || 		intf_mode == VK_LinkageMode'

Warning: verify failed: 'intf_mode == VK_BadMode || 		intf_mode == VK_InternalMode || 		intf_mode == VK_InMode || 		intf_mode == VK_InoutMode || 		intf_mode == VK_OutMode || 		intf_mode == VK_BufferMode || 		intf_mode == VK_LinkageMode'

Warning: verify failed: 'intf_mode == VK_BadMode || 		intf_mode == VK_InternalMode || 		intf_mode == VK_InMode || 		intf_mode == VK_InoutMode || 		intf_mode == VK_OutMode || 		intf_mode == VK_BufferMode || 		intf_mode == VK_LinkageMode'

Warning: verify failed: 'intf_mode == VK_BadMode || 		intf_mode == VK_InternalMode || 		intf_mode == VK_InMode || 		intf_mode == VK_InoutMode || 		intf_mode == VK_OutMode || 		intf_mode == VK_BufferMode || 		intf_mode == VK_LinkageMode'

Warning: verify failed: 'intf_mode == VK_BadMode || 		intf_mode == VK_InternalMode || 		intf_mode == VK_InMode || 		intf_mode == VK_InoutMode || 		intf_mode == VK_OutMode || 		intf_mode == VK_BufferMode || 		intf_mode == VK_LinkageMode'

Warning: verify failed: 'intf_mode == VK_BadMode || 		intf_mode == VK_InternalMode || 		intf_mode == VK_InMode || 		intf_mode == VK_InoutMode || 		intf_mode == VK_OutMode || 		intf_mode == VK_BufferMode || 		intf_mode == VK_LinkageMode'

Warning: verify failed: 'intf_mode == VK_BadMode || 		intf_mode == VK_InternalMode || 		intf_mode == VK_InMode || 		intf_mode == VK_InoutMode || 		intf_mode == VK_OutMode || 		intf_mode == VK_BufferMode || 		intf_mode == VK_LinkageMode'

Warning: verify failed: 'intf_mode == VK_BadMode || 		intf_mode == VK_InternalMode || 		intf_mode == VK_InMode || 		intf_mode == VK_InoutMode || 		intf_mode == VK_OutMode || 		intf_mode == VK_BufferMode || 		intf_mode == VK_LinkageMode'

Warning: verify failed: 'intf_mode == VK_BadMode || 		intf_mode == VK_InternalMode || 		intf_mode == VK_InMode || 		intf_mode == VK_InoutMode || 		intf_mode == VK_OutMode || 		intf_mode == VK_BufferMode || 		intf_mode == VK_LinkageMode'

Warning: verify failed: 'intf_mode == VK_BadMode || 		intf_mode == VK_InternalMode || 		intf_mode == VK_InMode || 		intf_mode == VK_InoutMode || 		intf_mode == VK_OutMode || 		intf_mode == VK_BufferMode || 		intf_mode == VK_LinkageMode'

Warning: verify failed: 'intf_mode == VK_BadMode || 		intf_mode == VK_InternalMode || 		intf_mode == VK_InMode || 		intf_mode == VK_InoutMode || 		intf_mode == VK_OutMode || 		intf_mode == VK_BufferMode || 		intf_mode == VK_LinkageMode'

Warning: verify failed: 'intf_mode == VK_BadMode || 		intf_mode == VK_InternalMode || 		intf_mode == VK_InMode || 		intf_mode == VK_InoutMode || 		intf_mode == VK_OutMode || 		intf_mode == VK_BufferMode || 		intf_mode == VK_LinkageMode'

Warning: verify failed: 'intf_mode == VK_BadMode || 		intf_mode == VK_InternalMode || 		intf_mode == VK_InMode || 		intf_mode == VK_InoutMode || 		intf_mode == VK_OutMode || 		intf_mode == VK_BufferMode || 		intf_mode == VK_LinkageMode'

Warning: verify failed: 'intf_mode == VK_BadMode || 		intf_mode == VK_InternalMode || 		intf_mode == VK_InMode || 		intf_mode == VK_InoutMode || 		intf_mode == VK_OutMode || 		intf_mode == VK_BufferMode || 		intf_mode == VK_LinkageMode'

Warning: verify failed: 'intf_mode == VK_BadMode || 		intf_mode == VK_InternalMode || 		intf_mode == VK_InMode || 		intf_mode == VK_InoutMode || 		intf_mode == VK_OutMode || 		intf_mode == VK_BufferMode || 		intf_mode == VK_LinkageMode'

Warning: verify failed: 'intf_mode == VK_BadMode || 		intf_mode == VK_InternalMode || 		intf_mode == VK_InMode || 		intf_mode == VK_InoutMode || 		intf_mode == VK_OutMode || 		intf_mode == VK_BufferMode || 		intf_mode == VK_LinkageMode'

Warning: verify failed: 'intf_mode == VK_BadMode || 		intf_mode == VK_InternalMode || 		intf_mode == VK_InMode || 		intf_mode == VK_InoutMode || 		intf_mode == VK_OutMode || 		intf_mode == VK_BufferMode || 		intf_mode == VK_LinkageMode'

Warning: verify failed: 'intf_mode == VK_BadMode || 		intf_mode == VK_InternalMode || 		intf_mode == VK_InMode || 		intf_mode == VK_InoutMode || 		intf_mode == VK_OutMode || 		intf_mode == VK_BufferMode || 		intf_mode == VK_LinkageMode'

Warning: verify failed: 'intf_mode == VK_BadMode || 		intf_mode == VK_InternalMode || 		intf_mode == VK_InMode || 		intf_mode == VK_InoutMode || 		intf_mode == VK_OutMode || 		intf_mode == VK_BufferMode || 		intf_mode == VK_LinkageMode'

Warning: verify failed: 'intf_mode == VK_BadMode || 		intf_mode == VK_InternalMode || 		intf_mode == VK_InMode || 		intf_mode == VK_InoutMode || 		intf_mode == VK_OutMode || 		intf_mode == VK_BufferMode || 		intf_mode == VK_LinkageMode'

Warning: verify failed: 'intf_mode == VK_BadMode || 		intf_mode == VK_InternalMode || 		intf_mode == VK_InMode || 		intf_mode == VK_InoutMode || 		intf_mode == VK_OutMode || 		intf_mode == VK_BufferMode || 		intf_mode == VK_LinkageMode'

Warning: verify failed: 'intf_mode == VK_BadMode || 		intf_mode == VK_InternalMode || 		intf_mode == VK_InMode || 		intf_mode == VK_InoutMode || 		intf_mode == VK_OutMode || 		intf_mode == VK_BufferMode || 		intf_mode == VK_LinkageMode'

Warning: verify failed: 'intf_mode == VK_BadMode || 		intf_mode == VK_InternalMode || 		intf_mode == VK_InMode || 		intf_mode == VK_InoutMode || 		intf_mode == VK_OutMode || 		intf_mode == VK_BufferMode || 		intf_mode == VK_LinkageMode'

Warning: verify failed: 'intf_mode == VK_BadMode || 		intf_mode == VK_InternalMode || 		intf_mode == VK_InMode || 		intf_mode == VK_InoutMode || 		intf_mode == VK_OutMode || 		intf_mode == VK_BufferMode || 		intf_mode == VK_LinkageMode'

Warning: verify failed: 'intf_mode == VK_BadMode || 		intf_mode == VK_InternalMode || 		intf_mode == VK_InMode || 		intf_mode == VK_InoutMode || 		intf_mode == VK_OutMode || 		intf_mode == VK_BufferMode || 		intf_mode == VK_LinkageMode'

Warning: verify failed: 'intf_mode == VK_BadMode || 		intf_mode == VK_InternalMode || 		intf_mode == VK_InMode || 		intf_mode == VK_InoutMode || 		intf_mode == VK_OutMode || 		intf_mode == VK_BufferMode || 		intf_mode == VK_LinkageMode'

Warning: verify failed: 'intf_mode == VK_BadMode || 		intf_mode == VK_InternalMode || 		intf_mode == VK_InMode || 		intf_mode == VK_InoutMode || 		intf_mode == VK_OutMode || 		intf_mode == VK_BufferMode || 		intf_mode == VK_LinkageMode'

Warning: verify failed: 'intf_mode == VK_BadMode || 		intf_mode == VK_InternalMode || 		intf_mode == VK_InMode || 		intf_mode == VK_InoutMode || 		intf_mode == VK_OutMode || 		intf_mode == VK_BufferMode || 		intf_mode == VK_LinkageMode'

Warning: verify failed: 'intf_mode == VK_BadMode || 		intf_mode == VK_InternalMode || 		intf_mode == VK_InMode || 		intf_mode == VK_InoutMode || 		intf_mode == VK_OutMode || 		intf_mode == VK_BufferMode || 		intf_mode == VK_LinkageMode'

Warning: verify failed: 'intf_mode == VK_BadMode || 		intf_mode == VK_InternalMode || 		intf_mode == VK_InMode || 		intf_mode == VK_InoutMode || 		intf_mode == VK_OutMode || 		intf_mode == VK_BufferMode || 		intf_mode == VK_LinkageMode'

Warning: verify failed: 'intf_mode == VK_BadMode || 		intf_mode == VK_InternalMode || 		intf_mode == VK_InMode || 		intf_mode == VK_InoutMode || 		intf_mode == VK_OutMode || 		intf_mode == VK_BufferMode || 		intf_mode == VK_LinkageMode'

Warning: verify failed: 'intf_mode == VK_BadMode || 		intf_mode == VK_InternalMode || 		intf_mode == VK_InMode || 		intf_mode == VK_InoutMode || 		intf_mode == VK_OutMode || 		intf_mode == VK_BufferMode || 		intf_mode == VK_LinkageMode'

Warning: verify failed: 'intf_mode == VK_BadMode || 		intf_mode == VK_InternalMode || 		intf_mode == VK_InMode || 		intf_mode == VK_InoutMode || 		intf_mode == VK_OutMode || 		intf_mode == VK_BufferMode || 		intf_mode == VK_LinkageMode'

Warning: verify failed: 'intf_mode == VK_BadMode || 		intf_mode == VK_InternalMode || 		intf_mode == VK_InMode || 		intf_mode == VK_InoutMode || 		intf_mode == VK_OutMode || 		intf_mode == VK_BufferMode || 		intf_mode == VK_LinkageMode'

Warning: verify failed: 'intf_mode == VK_BadMode || 		intf_mode == VK_InternalMode || 		intf_mode == VK_InMode || 		intf_mode == VK_InoutMode || 		intf_mode == VK_OutMode || 		intf_mode == VK_BufferMode || 		intf_mode == VK_LinkageMode'

Warning: verify failed: 'intf_mode == VK_BadMode || 		intf_mode == VK_InternalMode || 		intf_mode == VK_InMode || 		intf_mode == VK_InoutMode || 		intf_mode == VK_OutMode || 		intf_mode == VK_BufferMode || 		intf_mode == VK_LinkageMode'

Warning: verify failed: 'intf_mode == VK_BadMode || 		intf_mode == VK_InternalMode || 		intf_mode == VK_InMode || 		intf_mode == VK_InoutMode || 		intf_mode == VK_OutMode || 		intf_mode == VK_BufferMode || 		intf_mode == VK_LinkageMode'

Warning: verify failed: 'intf_mode == VK_BadMode || 		intf_mode == VK_InternalMode || 		intf_mode == VK_InMode || 		intf_mode == VK_InoutMode || 		intf_mode == VK_OutMode || 		intf_mode == VK_BufferMode || 		intf_mode == VK_LinkageMode'

Warning: verify failed: 'intf_mode == VK_BadMode || 		intf_mode == VK_InternalMode || 		intf_mode == VK_InMode || 		intf_mode == VK_InoutMode || 		intf_mode == VK_OutMode || 		intf_mode == VK_BufferMode || 		intf_mode == VK_LinkageMode'

Warning: verify failed: 'intf_mode == VK_BadMode || 		intf_mode == VK_InternalMode || 		intf_mode == VK_InMode || 		intf_mode == VK_InoutMode || 		intf_mode == VK_OutMode || 		intf_mode == VK_BufferMode || 		intf_mode == VK_LinkageMode'

Warning: verify failed: 'intf_mode == VK_BadMode || 		intf_mode == VK_InternalMode || 		intf_mode == VK_InMode || 		intf_mode == VK_InoutMode || 		intf_mode == VK_OutMode || 		intf_mode == VK_BufferMode || 		intf_mode == VK_LinkageMode'

Warning: verify failed: 'intf_mode == VK_BadMode || 		intf_mode == VK_InternalMode || 		intf_mode == VK_InMode || 		intf_mode == VK_InoutMode || 		intf_mode == VK_OutMode || 		intf_mode == VK_BufferMode || 		intf_mode == VK_LinkageMode'

Warning: verify failed: 'intf_mode == VK_BadMode || 		intf_mode == VK_InternalMode || 		intf_mode == VK_InMode || 		intf_mode == VK_InoutMode || 		intf_mode == VK_OutMode || 		intf_mode == VK_BufferMode || 		intf_mode == VK_LinkageMode'

Warning: verify failed: 'intf_mode == VK_BadMode || 		intf_mode == VK_InternalMode || 		intf_mode == VK_InMode || 		intf_mode == VK_InoutMode || 		intf_mode == VK_OutMode || 		intf_mode == VK_BufferMode || 		intf_mode == VK_LinkageMode'

Warning: verify failed: 'intf_mode == VK_BadMode || 		intf_mode == VK_InternalMode || 		intf_mode == VK_InMode || 		intf_mode == VK_InoutMode || 		intf_mode == VK_OutMode || 		intf_mode == VK_BufferMode || 		intf_mode == VK_LinkageMode'

Warning: verify failed: 'intf_mode == VK_BadMode || 		intf_mode == VK_InternalMode || 		intf_mode == VK_InMode || 		intf_mode == VK_InoutMode || 		intf_mode == VK_OutMode || 		intf_mode == VK_BufferMode || 		intf_mode == VK_LinkageMode'

Warning: verify failed: 'intf_mode == VK_BadMode || 		intf_mode == VK_InternalMode || 		intf_mode == VK_InMode || 		intf_mode == VK_InoutMode || 		intf_mode == VK_OutMode || 		intf_mode == VK_BufferMode || 		intf_mode == VK_LinkageMode'

Warning: verify failed: 'intf_mode == VK_BadMode || 		intf_mode == VK_InternalMode || 		intf_mode == VK_InMode || 		intf_mode == VK_InoutMode || 		intf_mode == VK_OutMode || 		intf_mode == VK_BufferMode || 		intf_mode == VK_LinkageMode'

Warning: verify failed: 'intf_mode == VK_BadMode || 		intf_mode == VK_InternalMode || 		intf_mode == VK_InMode || 		intf_mode == VK_InoutMode || 		intf_mode == VK_OutMode || 		intf_mode == VK_BufferMode || 		intf_mode == VK_LinkageMode'

Warning: verify failed: 'intf_mode == VK_BadMode || 		intf_mode == VK_InternalMode || 		intf_mode == VK_InMode || 		intf_mode == VK_InoutMode || 		intf_mode == VK_OutMode || 		intf_mode == VK_BufferMode || 		intf_mode == VK_LinkageMode'

Warning: verify failed: 'intf_mode == VK_BadMode || 		intf_mode == VK_InternalMode || 		intf_mode == VK_InMode || 		intf_mode == VK_InoutMode || 		intf_mode == VK_OutMode || 		intf_mode == VK_BufferMode || 		intf_mode == VK_LinkageMode'

Warning: verify failed: 'intf_mode == VK_BadMode || 		intf_mode == VK_InternalMode || 		intf_mode == VK_InMode || 		intf_mode == VK_InoutMode || 		intf_mode == VK_OutMode || 		intf_mode == VK_BufferMode || 		intf_mode == VK_LinkageMode'

Warning: verify failed: 'intf_mode == VK_BadMode || 		intf_mode == VK_InternalMode || 		intf_mode == VK_InMode || 		intf_mode == VK_InoutMode || 		intf_mode == VK_OutMode || 		intf_mode == VK_BufferMode || 		intf_mode == VK_LinkageMode'

Warning: verify failed: 'intf_mode == VK_BadMode || 		intf_mode == VK_InternalMode || 		intf_mode == VK_InMode || 		intf_mode == VK_InoutMode || 		intf_mode == VK_OutMode || 		intf_mode == VK_BufferMode || 		intf_mode == VK_LinkageMode'

Warning: verify failed: 'intf_mode == VK_BadMode || 		intf_mode == VK_InternalMode || 		intf_mode == VK_InMode || 		intf_mode == VK_InoutMode || 		intf_mode == VK_OutMode || 		intf_mode == VK_BufferMode || 		intf_mode == VK_LinkageMode'

Warning: verify failed: 'intf_mode == VK_BadMode || 		intf_mode == VK_InternalMode || 		intf_mode == VK_InMode || 		intf_mode == VK_InoutMode || 		intf_mode == VK_OutMode || 		intf_mode == VK_BufferMode || 		intf_mode == VK_LinkageMode'

Warning: verify failed: 'intf_mode == VK_BadMode || 		intf_mode == VK_InternalMode || 		intf_mode == VK_InMode || 		intf_mode == VK_InoutMode || 		intf_mode == VK_OutMode || 		intf_mode == VK_BufferMode || 		intf_mode == VK_LinkageMode'

Warning: verify failed: 'intf_mode == VK_BadMode || 		intf_mode == VK_InternalMode || 		intf_mode == VK_InMode || 		intf_mode == VK_InoutMode || 		intf_mode == VK_OutMode || 		intf_mode == VK_BufferMode || 		intf_mode == VK_LinkageMode'

Warning: verify failed: 'intf_mode == VK_BadMode || 		intf_mode == VK_InternalMode || 		intf_mode == VK_InMode || 		intf_mode == VK_InoutMode || 		intf_mode == VK_OutMode || 		intf_mode == VK_BufferMode || 		intf_mode == VK_LinkageMode'

Warning: verify failed: 'intf_mode == VK_BadMode || 		intf_mode == VK_InternalMode || 		intf_mode == VK_InMode || 		intf_mode == VK_InoutMode || 		intf_mode == VK_OutMode || 		intf_mode == VK_BufferMode || 		intf_mode == VK_LinkageMode'

Warning: verify failed: 'intf_mode == VK_BadMode || 		intf_mode == VK_InternalMode || 		intf_mode == VK_InMode || 		intf_mode == VK_InoutMode || 		intf_mode == VK_OutMode || 		intf_mode == VK_BufferMode || 		intf_mode == VK_LinkageMode'

Warning: verify failed: 'intf_mode == VK_BadMode || 		intf_mode == VK_InternalMode || 		intf_mode == VK_InMode || 		intf_mode == VK_InoutMode || 		intf_mode == VK_OutMode || 		intf_mode == VK_BufferMode || 		intf_mode == VK_LinkageMode'

Warning: verify failed: 'intf_mode == VK_BadMode || 		intf_mode == VK_InternalMode || 		intf_mode == VK_InMode || 		intf_mode == VK_InoutMode || 		intf_mode == VK_OutMode || 		intf_mode == VK_BufferMode || 		intf_mode == VK_LinkageMode'

Warning: verify failed: 'intf_mode == VK_BadMode || 		intf_mode == VK_InternalMode || 		intf_mode == VK_InMode || 		intf_mode == VK_InoutMode || 		intf_mode == VK_OutMode || 		intf_mode == VK_BufferMode || 		intf_mode == VK_LinkageMode'

Warning: verify failed: 'intf_mode == VK_BadMode || 		intf_mode == VK_InternalMode || 		intf_mode == VK_InMode || 		intf_mode == VK_InoutMode || 		intf_mode == VK_OutMode || 		intf_mode == VK_BufferMode || 		intf_mode == VK_LinkageMode'

Warning: verify failed: 'intf_mode == VK_BadMode || 		intf_mode == VK_InternalMode || 		intf_mode == VK_InMode || 		intf_mode == VK_InoutMode || 		intf_mode == VK_OutMode || 		intf_mode == VK_BufferMode || 		intf_mode == VK_LinkageMode'

Warning: verify failed: 'intf_mode == VK_BadMode || 		intf_mode == VK_InternalMode || 		intf_mode == VK_InMode || 		intf_mode == VK_InoutMode || 		intf_mode == VK_OutMode || 		intf_mode == VK_BufferMode || 		intf_mode == VK_LinkageMode'

Warning: verify failed: 'intf_mode == VK_BadMode || 		intf_mode == VK_InternalMode || 		intf_mode == VK_InMode || 		intf_mode == VK_InoutMode || 		intf_mode == VK_OutMode || 		intf_mode == VK_BufferMode || 		intf_mode == VK_LinkageMode'

Warning: verify failed: 'intf_mode == VK_BadMode || 		intf_mode == VK_InternalMode || 		intf_mode == VK_InMode || 		intf_mode == VK_InoutMode || 		intf_mode == VK_OutMode || 		intf_mode == VK_BufferMode || 		intf_mode == VK_LinkageMode'

Warning: verify failed: 'intf_mode == VK_BadMode || 		intf_mode == VK_InternalMode || 		intf_mode == VK_InMode || 		intf_mode == VK_InoutMode || 		intf_mode == VK_OutMode || 		intf_mode == VK_BufferMode || 		intf_mode == VK_LinkageMode'

Warning: verify failed: 'intf_mode == VK_BadMode || 		intf_mode == VK_InternalMode || 		intf_mode == VK_InMode || 		intf_mode == VK_InoutMode || 		intf_mode == VK_OutMode || 		intf_mode == VK_BufferMode || 		intf_mode == VK_LinkageMode'

Warning: verify failed: 'intf_mode == VK_BadMode || 		intf_mode == VK_InternalMode || 		intf_mode == VK_InMode || 		intf_mode == VK_InoutMode || 		intf_mode == VK_OutMode || 		intf_mode == VK_BufferMode || 		intf_mode == VK_LinkageMode'

Warning: verify failed: 'intf_mode == VK_BadMode || 		intf_mode == VK_InternalMode || 		intf_mode == VK_InMode || 		intf_mode == VK_InoutMode || 		intf_mode == VK_OutMode || 		intf_mode == VK_BufferMode || 		intf_mode == VK_LinkageMode'

Warning: verify failed: 'intf_mode == VK_BadMode || 		intf_mode == VK_InternalMode || 		intf_mode == VK_InMode || 		intf_mode == VK_InoutMode || 		intf_mode == VK_OutMode || 		intf_mode == VK_BufferMode || 		intf_mode == VK_LinkageMode'

Warning: verify failed: 'intf_mode == VK_BadMode || 		intf_mode == VK_InternalMode || 		intf_mode == VK_InMode || 		intf_mode == VK_InoutMode || 		intf_mode == VK_OutMode || 		intf_mode == VK_BufferMode || 		intf_mode == VK_LinkageMode'

Warning: verify failed: 'intf_mode == VK_BadMode || 		intf_mode == VK_InternalMode || 		intf_mode == VK_InMode || 		intf_mode == VK_InoutMode || 		intf_mode == VK_OutMode || 		intf_mode == VK_BufferMode || 		intf_mode == VK_LinkageMode'

Warning: verify failed: 'intf_mode == VK_BadMode || 		intf_mode == VK_InternalMode || 		intf_mode == VK_InMode || 		intf_mode == VK_InoutMode || 		intf_mode == VK_OutMode || 		intf_mode == VK_BufferMode || 		intf_mode == VK_LinkageMode'

Warning: verify failed: 'intf_mode == VK_BadMode || 		intf_mode == VK_InternalMode || 		intf_mode == VK_InMode || 		intf_mode == VK_InoutMode || 		intf_mode == VK_OutMode || 		intf_mode == VK_BufferMode || 		intf_mode == VK_LinkageMode'

Warning: verify failed: 'intf_mode == VK_BadMode || 		intf_mode == VK_InternalMode || 		intf_mode == VK_InMode || 		intf_mode == VK_InoutMode || 		intf_mode == VK_OutMode || 		intf_mode == VK_BufferMode || 		intf_mode == VK_LinkageMode'

Warning: verify failed: 'intf_mode == VK_BadMode || 		intf_mode == VK_InternalMode || 		intf_mode == VK_InMode || 		intf_mode == VK_InoutMode || 		intf_mode == VK_OutMode || 		intf_mode == VK_BufferMode || 		intf_mode == VK_LinkageMode'

Warning: verify failed: 'intf_mode == VK_BadMode || 		intf_mode == VK_InternalMode || 		intf_mode == VK_InMode || 		intf_mode == VK_InoutMode || 		intf_mode == VK_OutMode || 		intf_mode == VK_BufferMode || 		intf_mode == VK_LinkageMode'

Warning: verify failed: 'intf_mode == VK_BadMode || 		intf_mode == VK_InternalMode || 		intf_mode == VK_InMode || 		intf_mode == VK_InoutMode || 		intf_mode == VK_OutMode || 		intf_mode == VK_BufferMode || 		intf_mode == VK_LinkageMode'

controller: initializing
s1_monitor: X"00000000"
s2_monitor: X"00000000"
dest_monitor: X"00000000"
controller: instruction fetch
DLX_bus_monitor: Command I-fetch from X"00000000", word
DLX_bus_monitor: Ready, instruction X"24010002" [ ADDUI    R1, R0, 2 ]
controller: decode, reg-read and PC incr
s2_monitor: X"00000004"
dest_monitor: X"00000004"
s2_monitor: X"00000000"
controller: execute
dest_monitor: X"00000000"
s2_monitor: X"00000002"
dest_monitor: X"00000002"
s2_monitor: X"00000000"
controller: memory access or branch completion
controller: write-back
controller: instruction fetch
DLX_bus_monitor: Command I-fetch from X"00000004", word
DLX_bus_monitor: Ready, instruction X"AC010028" [ SW       40(R0), R1 ]
controller: decode, reg-read and PC incr
s2_monitor: X"00000004"
dest_monitor: X"00000000"
dest_monitor: X"00000004"
s1_monitor: X"00000004"
dest_monitor: X"00000008"
s2_monitor: X"00000000"
s1_monitor: X"00000000"
controller: execute
dest_monitor: X"00000000"
s2_monitor: X"00000028"
dest_monitor: X"00000028"
s2_monitor: X"00000000"
controller: memory access or branch completion
dest_monitor: X"00000000"
s2_monitor: X"00000002"
dest_monitor: X"00000002"
s2_monitor: X"00000000"
DLX_bus_monitor: Command D-write to X"00000028", word, data X"00000002"
DLX_bus_monitor: Ready
controller: write-back
controller: instruction fetch
DLX_bus_monitor: Command I-fetch from X"00000008", word
DLX_bus_monitor: Ready, instruction X"2402000A" [ ADDUI    R2, R0, 10 ]
controller: decode, reg-read and PC incr
s2_monitor: X"00000004"
dest_monitor: X"00000000"
dest_monitor: X"00000004"
s1_monitor: X"00000008"
dest_monitor: X"0000000C"
s2_monitor: X"00000000"
s1_monitor: X"00000000"
controller: execute
dest_monitor: X"00000000"
s2_monitor: X"0000000A"
dest_monitor: X"0000000A"
s2_monitor: X"00000000"
controller: memory access or branch completion
controller: write-back
controller: instruction fetch
DLX_bus_monitor: Command I-fetch from X"0000000C", word
DLX_bus_monitor: Ready, instruction X"2C420001" [ SUBUI    R2, R2, 1 ]
controller: decode, reg-read and PC incr
s2_monitor: X"00000004"
dest_monitor: X"00000000"
dest_monitor: X"00000004"
s1_monitor: X"0000000C"
dest_monitor: X"00000010"
s2_monitor: X"00000000"
s1_monitor: X"00000000"
controller: execute
dest_monitor: X"00000000"
s2_monitor: X"00000001"
s1_monitor: X"0000000A"
dest_monitor: X"00000009"
s2_monitor: X"00000000"
s1_monitor: X"00000000"
controller: memory access or branch completion
controller: write-back
controller: instruction fetch
DLX_bus_monitor: Command I-fetch from X"00000010", word
DLX_bus_monitor: Ready, instruction X"1440FFF8" [ BNEZ     R2, -8 ]
controller: decode, reg-read and PC incr
s2_monitor: X"00000004"
dest_monitor: X"00000000"
dest_monitor: X"00000004"
s1_monitor: X"00000010"
dest_monitor: X"00000014"
s2_monitor: X"00000000"
s1_monitor: X"00000000"
controller: execute
dest_monitor: X"00000000"
s1_monitor: X"00000009"
dest_monitor: X"00000009"
s1_monitor: X"00000000"
controller: memory access or branch completion
dest_monitor: X"00000000"
s2_monitor: X"FFFFFFF8"
s1_monitor: X"00000014"
dest_monitor: X"0000000C"
s2_monitor: X"00000000"
s1_monitor: X"00000000"
controller: write-back
controller: instruction fetch
DLX_bus_monitor: Command I-fetch from X"0000000C", word
DLX_bus_monitor: Ready, instruction X"2C420001" [ SUBUI    R2, R2, 1 ]
controller: decode, reg-read and PC incr
s2_monitor: X"00000004"
dest_monitor: X"00000000"
dest_monitor: X"00000004"
s1_monitor: X"0000000C"
dest_monitor: X"00000010"
s2_monitor: X"00000000"
s1_monitor: X"00000000"
controller: execute
dest_monitor: X"00000000"
s2_monitor: X"00000001"
s1_monitor: X"00000009"
dest_monitor: X"00000008"
s2_monitor: X"00000000"
s1_monitor: X"00000000"
controller: memory access or branch completion
controller: write-back
controller: instruction fetch
DLX_bus_monitor: Command I-fetch from X"00000010", word
DLX_bus_monitor: Ready, instruction X"1440FFF8" [ BNEZ     R2, -8 ]
controller: decode, reg-read and PC incr
s2_monitor: X"00000004"
dest_monitor: X"00000000"
dest_monitor: X"00000004"
s1_monitor: X"00000010"
dest_monitor: X"00000014"
s2_monitor: X"00000000"
s1_monitor: X"00000000"
controller: execute
dest_monitor: X"00000000"
s1_monitor: X"00000008"
dest_monitor: X"00000008"
s1_monitor: X"00000000"
controller: memory access or branch completion
dest_monitor: X"00000000"
s2_monitor: X"FFFFFFF8"
s1_monitor: X"00000014"
dest_monitor: X"0000000C"
s2_monitor: X"00000000"
s1_monitor: X"00000000"
controller: write-back
controller: instruction fetch
DLX_bus_monitor: Command I-fetch from X"0000000C", word
DLX_bus_monitor: Ready, instruction X"2C420001" [ SUBUI    R2, R2, 1 ]
controller: decode, reg-read and PC incr
s2_monitor: X"00000004"
dest_monitor: X"00000000"
dest_monitor: X"00000004"
s1_monitor: X"0000000C"
dest_monitor: X"00000010"
s2_monitor: X"00000000"
s1_monitor: X"00000000"
controller: execute
dest_monitor: X"00000000"
s2_monitor: X"00000001"
s1_monitor: X"00000008"
dest_monitor: X"00000007"
s2_monitor: X"00000000"
s1_monitor: X"00000000"
controller: memory access or branch completion
controller: write-back
controller: instruction fetch
DLX_bus_monitor: Command I-fetch from X"00000010", word
DLX_bus_monitor: Ready, instruction X"1440FFF8" [ BNEZ     R2, -8 ]
controller: decode, reg-read and PC incr
s2_monitor: X"00000004"
dest_monitor: X"00000000"
dest_monitor: X"00000004"
s1_monitor: X"00000010"
dest_monitor: X"00000014"
s2_monitor: X"00000000"
s1_monitor: X"00000000"
controller: execute
dest_monitor: X"00000000"
s1_monitor: X"00000007"
dest_monitor: X"00000007"
s1_monitor: X"00000000"
controller: memory access or branch completion
dest_monitor: X"00000000"
s2_monitor: X"FFFFFFF8"
s1_monitor: X"00000014"
dest_monitor: X"0000000C"
s2_monitor: X"00000000"
s1_monitor: X"00000000"
controller: write-back
controller: instruction fetch
DLX_bus_monitor: Command I-fetch from X"0000000C", word
DLX_bus_monitor: Ready, instruction X"2C420001" [ SUBUI    R2, R2, 1 ]
controller: decode, reg-read and PC incr
s2_monitor: X"00000004"
dest_monitor: X"00000000"
dest_monitor: X"00000004"
s1_monitor: X"0000000C"
dest_monitor: X"00000010"
s2_monitor: X"00000000"
s1_monitor: X"00000000"
controller: execute
dest_monitor: X"00000000"
s2_monitor: X"00000001"
s1_monitor: X"00000007"
dest_monitor: X"00000006"
s2_monitor: X"00000000"
s1_monitor: X"00000000"
controller: memory access or branch completion
controller: write-back
controller: instruction fetch
DLX_bus_monitor: Command I-fetch from X"00000010", word
DLX_bus_monitor: Ready, instruction X"1440FFF8" [ BNEZ     R2, -8 ]
controller: decode, reg-read and PC incr
s2_monitor: X"00000004"
dest_monitor: X"00000000"
dest_monitor: X"00000004"
s1_monitor: X"00000010"
dest_monitor: X"00000014"
s2_monitor: X"00000000"
s1_monitor: X"00000000"
controller: execute
dest_monitor: X"00000000"
s1_monitor: X"00000006"
dest_monitor: X"00000006"
s1_monitor: X"00000000"
controller: memory access or branch completion
dest_monitor: X"00000000"
s2_monitor: X"FFFFFFF8"
s1_monitor: X"00000014"
dest_monitor: X"0000000C"
s2_monitor: X"00000000"
s1_monitor: X"00000000"
controller: write-back
controller: instruction fetch
DLX_bus_monitor: Command I-fetch from X"0000000C", word
DLX_bus_monitor: Ready, instruction X"2C420001" [ SUBUI    R2, R2, 1 ]
controller: decode, reg-read and PC incr
s2_monitor: X"00000004"
dest_monitor: X"00000000"
dest_monitor: X"00000004"
s1_monitor: X"0000000C"
dest_monitor: X"00000010"
s2_monitor: X"00000000"
s1_monitor: X"00000000"
controller: execute
dest_monitor: X"00000000"
s2_monitor: X"00000001"
s1_monitor: X"00000006"
dest_monitor: X"00000005"
s2_monitor: X"00000000"
s1_monitor: X"00000000"
controller: memory access or branch completion
controller: write-back
controller: instruction fetch
DLX_bus_monitor: Command I-fetch from X"00000010", word
DLX_bus_monitor: Ready, instruction X"1440FFF8" [ BNEZ     R2, -8 ]
controller: decode, reg-read and PC incr
s2_monitor: X"00000004"
dest_monitor: X"00000000"
dest_monitor: X"00000004"
s1_monitor: X"00000010"
dest_monitor: X"00000014"
s2_monitor: X"00000000"
s1_monitor: X"00000000"
controller: execute
dest_monitor: X"00000000"
s1_monitor: X"00000005"
dest_monitor: X"00000005"
s1_monitor: X"00000000"
controller: memory access or branch completion
dest_monitor: X"00000000"
s2_monitor: X"FFFFFFF8"
s1_monitor: X"00000014"
dest_monitor: X"0000000C"
s2_monitor: X"00000000"
s1_monitor: X"00000000"
controller: write-back
controller: instruction fetch
DLX_bus_monitor: Command I-fetch from X"0000000C", word
DLX_bus_monitor: Ready, instruction X"2C420001" [ SUBUI    R2, R2, 1 ]
controller: decode, reg-read and PC incr
s2_monitor: X"00000004"
dest_monitor: X"00000000"
dest_monitor: X"00000004"
s1_monitor: X"0000000C"
dest_monitor: X"00000010"
s2_monitor: X"00000000"
s1_monitor: X"00000000"
controller: execute
dest_monitor: X"00000000"
s2_monitor: X"00000001"
s1_monitor: X"00000005"
dest_monitor: X"00000004"
s2_monitor: X"00000000"
s1_monitor: X"00000000"
controller: memory access or branch completion
controller: write-back
controller: instruction fetch
DLX_bus_monitor: Command I-fetch from X"00000010", word
DLX_bus_monitor: Ready, instruction X"1440FFF8" [ BNEZ     R2, -8 ]
controller: decode, reg-read and PC incr
s2_monitor: X"00000004"
dest_monitor: X"00000000"
dest_monitor: X"00000004"
s1_monitor: X"00000010"
dest_monitor: X"00000014"
s2_monitor: X"00000000"
s1_monitor: X"00000000"
controller: execute
dest_monitor: X"00000000"
s1_monitor: X"00000004"
dest_monitor: X"00000004"
s1_monitor: X"00000000"
controller: memory access or branch completion
dest_monitor: X"00000000"
s2_monitor: X"FFFFFFF8"
s1_monitor: X"00000014"
dest_monitor: X"0000000C"
s2_monitor: X"00000000"
s1_monitor: X"00000000"
controller: write-back
controller: instruction fetch
DLX_bus_monitor: Command I-fetch from X"0000000C", word
DLX_bus_monitor: Ready, instruction X"2C420001" [ SUBUI    R2, R2, 1 ]
controller: decode, reg-read and PC incr
s2_monitor: X"00000004"
dest_monitor: X"00000000"
dest_monitor: X"00000004"
s1_monitor: X"0000000C"
dest_monitor: X"00000010"
s2_monitor: X"00000000"
s1_monitor: X"00000000"
controller: execute
dest_monitor: X"00000000"
s2_monitor: X"00000001"
s1_monitor: X"00000004"
dest_monitor: X"00000003"
s2_monitor: X"00000000"
s1_monitor: X"00000000"
controller: memory access or branch completion
controller: write-back
controller: instruction fetch
DLX_bus_monitor: Command I-fetch from X"00000010", word
DLX_bus_monitor: Ready, instruction X"1440FFF8" [ BNEZ     R2, -8 ]
controller: decode, reg-read and PC incr
s2_monitor: X"00000004"
dest_monitor: X"00000000"
dest_monitor: X"00000004"
s1_monitor: X"00000010"
dest_monitor: X"00000014"
s2_monitor: X"00000000"
s1_monitor: X"00000000"
controller: execute
dest_monitor: X"00000000"
s1_monitor: X"00000003"
dest_monitor: X"00000003"
s1_monitor: X"00000000"
controller: memory access or branch completion
dest_monitor: X"00000000"
s2_monitor: X"FFFFFFF8"
s1_monitor: X"00000014"
dest_monitor: X"0000000C"
s2_monitor: X"00000000"
s1_monitor: X"00000000"
controller: write-back
controller: instruction fetch
DLX_bus_monitor: Command I-fetch from X"0000000C", word
DLX_bus_monitor: Ready, instruction X"2C420001" [ SUBUI    R2, R2, 1 ]
controller: decode, reg-read and PC incr
s2_monitor: X"00000004"
dest_monitor: X"00000000"
dest_monitor: X"00000004"
s1_monitor: X"0000000C"
dest_monitor: X"00000010"
s2_monitor: X"00000000"
s1_monitor: X"00000000"
controller: execute
dest_monitor: X"00000000"
s2_monitor: X"00000001"
s1_monitor: X"00000003"
dest_monitor: X"00000002"
s2_monitor: X"00000000"
s1_monitor: X"00000000"
controller: memory access or branch completion
controller: write-back
controller: instruction fetch
DLX_bus_monitor: Command I-fetch from X"00000010", word
DLX_bus_monitor: Ready, instruction X"1440FFF8" [ BNEZ     R2, -8 ]
controller: decode, reg-read and PC incr
s2_monitor: X"00000004"
dest_monitor: X"00000000"
dest_monitor: X"00000004"
s1_monitor: X"00000010"
dest_monitor: X"00000014"
s2_monitor: X"00000000"
s1_monitor: X"00000000"
controller: execute
dest_monitor: X"00000000"
s1_monitor: X"00000002"
dest_monitor: X"00000002"
s1_monitor: X"00000000"
controller: memory access or branch completion
dest_monitor: X"00000000"
s2_monitor: X"FFFFFFF8"
s1_monitor: X"00000014"
dest_monitor: X"0000000C"
s2_monitor: X"00000000"
s1_monitor: X"00000000"
controller: write-back
controller: instruction fetch
DLX_bus_monitor: Command I-fetch from X"0000000C", word
DLX_bus_monitor: Ready, instruction X"2C420001" [ SUBUI    R2, R2, 1 ]
controller: decode, reg-read and PC incr
s2_monitor: X"00000004"
dest_monitor: X"00000000"
dest_monitor: X"00000004"
s1_monitor: X"0000000C"
dest_monitor: X"00000010"
s2_monitor: X"00000000"
s1_monitor: X"00000000"
controller: execute
dest_monitor: X"00000000"
s2_monitor: X"00000001"
s1_monitor: X"00000002"
dest_monitor: X"00000001"
s2_monitor: X"00000000"
s1_monitor: X"00000000"
controller: memory access or branch completion
controller: write-back
controller: instruction fetch
DLX_bus_monitor: Command I-fetch from X"00000010", word
DLX_bus_monitor: Ready, instruction X"1440FFF8" [ BNEZ     R2, -8 ]
controller: decode, reg-read and PC incr
s2_monitor: X"00000004"
dest_monitor: X"00000000"
dest_monitor: X"00000004"
s1_monitor: X"00000010"
dest_monitor: X"00000014"
s2_monitor: X"00000000"
s1_monitor: X"00000000"
controller: execute
dest_monitor: X"00000000"
s1_monitor: X"00000001"
dest_monitor: X"00000001"
s1_monitor: X"00000000"
controller: memory access or branch completion
dest_monitor: X"00000000"
s2_monitor: X"FFFFFFF8"
s1_monitor: X"00000014"
dest_monitor: X"0000000C"
s2_monitor: X"00000000"
s1_monitor: X"00000000"
controller: write-back
controller: instruction fetch
DLX_bus_monitor: Command I-fetch from X"0000000C", word
DLX_bus_monitor: Ready, instruction X"2C420001" [ SUBUI    R2, R2, 1 ]
controller: decode, reg-read and PC incr
s2_monitor: X"00000004"
dest_monitor: X"00000000"
dest_monitor: X"00000004"
s1_monitor: X"0000000C"
dest_monitor: X"00000010"
s2_monitor: X"00000000"
s1_monitor: X"00000000"
controller: execute
dest_monitor: X"00000000"
s2_monitor: X"00000001"
s1_monitor: X"00000001"
s2_monitor: X"00000000"
s1_monitor: X"00000000"
controller: memory access or branch completion
controller: write-back
controller: instruction fetch
DLX_bus_monitor: Command I-fetch from X"00000010", word
DLX_bus_monitor: Ready, instruction X"1440FFF8" [ BNEZ     R2, -8 ]
controller: decode, reg-read and PC incr
s2_monitor: X"00000004"
dest_monitor: X"00000004"
s1_monitor: X"00000010"
dest_monitor: X"00000014"
s2_monitor: X"00000000"
s1_monitor: X"00000000"
controller: execute
dest_monitor: X"00000000"
controller: memory access or branch completion
controller: write-back
controller: instruction fetch
DLX_bus_monitor: Command I-fetch from X"00000014", word
DLX_bus_monitor: Ready, instruction X"8C010028" [ LW       R1, 40(R0) ]
controller: decode, reg-read and PC incr
s2_monitor: X"00000004"
dest_monitor: X"00000004"
s1_monitor: X"00000014"
dest_monitor: X"00000018"
s2_monitor: X"00000000"
s1_monitor: X"00000000"
controller: execute
dest_monitor: X"00000000"
s2_monitor: X"00000028"
dest_monitor: X"00000028"
s2_monitor: X"00000000"
controller: memory access or branch completion
DLX_bus_monitor: Command D-read from X"00000028", word
DLX_bus_monitor: Ready, data X"00000002"
dest_monitor: X"00000000"
s1_monitor: X"00000002"
dest_monitor: X"00000002"
s1_monitor: X"00000000"
controller: write-back
controller: instruction fetch
DLX_bus_monitor: Command I-fetch from X"00000018", word
DLX_bus_monitor: Ready, instruction X"2C210001" [ SUBUI    R1, R1, 1 ]
controller: decode, reg-read and PC incr
s2_monitor: X"00000004"
dest_monitor: X"00000000"
dest_monitor: X"00000004"
s1_monitor: X"00000018"
dest_monitor: X"0000001C"
s2_monitor: X"00000000"
s1_monitor: X"00000000"
controller: execute
dest_monitor: X"00000000"
s2_monitor: X"00000001"
s1_monitor: X"00000002"
dest_monitor: X"00000001"
s2_monitor: X"00000000"
s1_monitor: X"00000000"
controller: memory access or branch completion
controller: write-back
controller: instruction fetch
DLX_bus_monitor: Command I-fetch from X"0000001C", word
DLX_bus_monitor: Ready, instruction X"AC010028" [ SW       40(R0), R1 ]
controller: decode, reg-read and PC incr
s2_monitor: X"00000004"
dest_monitor: X"00000000"
dest_monitor: X"00000004"
s1_monitor: X"0000001C"
dest_monitor: X"00000020"
s2_monitor: X"00000000"
s1_monitor: X"00000000"
controller: execute
dest_monitor: X"00000000"
s2_monitor: X"00000028"
dest_monitor: X"00000028"
s2_monitor: X"00000000"
controller: memory access or branch completion
dest_monitor: X"00000000"
s2_monitor: X"00000001"
dest_monitor: X"00000001"
s2_monitor: X"00000000"
DLX_bus_monitor: Command D-write to X"00000028", word, data X"00000001"
DLX_bus_monitor: Ready
controller: write-back
controller: instruction fetch
DLX_bus_monitor: Command I-fetch from X"00000020", word
DLX_bus_monitor: Ready, instruction X"1420FFE4" [ BNEZ     R1, -28 ]
controller: decode, reg-read and PC incr
s2_monitor: X"00000004"
dest_monitor: X"00000000"
dest_monitor: X"00000004"
s1_monitor: X"00000020"
dest_monitor: X"00000024"
s2_monitor: X"00000000"
s1_monitor: X"00000000"
controller: execute
dest_monitor: X"00000000"
s1_monitor: X"00000001"
dest_monitor: X"00000001"
s1_monitor: X"00000000"
controller: memory access or branch completion
dest_monitor: X"00000000"
s2_monitor: X"FFFFFFE4"
s1_monitor: X"00000024"
dest_monitor: X"00000008"
s2_monitor: X"00000000"
s1_monitor: X"00000000"
controller: write-back
controller: instruction fetch
DLX_bus_monitor: Command I-fetch from X"00000008", word
DLX_bus_monitor: Ready, instruction X"2402000A" [ ADDUI    R2, R0, 10 ]
controller: decode, reg-read and PC incr
s2_monitor: X"00000004"
dest_monitor: X"00000000"
dest_monitor: X"00000004"
s1_monitor: X"00000008"
dest_monitor: X"0000000C"
s2_monitor: X"00000000"
s1_monitor: X"00000000"
controller: execute
dest_monitor: X"00000000"
s2_monitor: X"0000000A"
dest_monitor: X"0000000A"
s2_monitor: X"00000000"
controller: memory access or branch completion
controller: write-back
controller: instruction fetch
DLX_bus_monitor: Command I-fetch from X"0000000C", word
DLX_bus_monitor: Ready, instruction X"2C420001" [ SUBUI    R2, R2, 1 ]
controller: decode, reg-read and PC incr
s2_monitor: X"00000004"
dest_monitor: X"00000000"
dest_monitor: X"00000004"
s1_monitor: X"0000000C"
dest_monitor: X"00000010"
s2_monitor: X"00000000"
s1_monitor: X"00000000"
controller: execute
dest_monitor: X"00000000"
s2_monitor: X"00000001"
s1_monitor: X"0000000A"
dest_monitor: X"00000009"
s2_monitor: X"00000000"
s1_monitor: X"00000000"
controller: memory access or branch completion
controller: write-back
controller: instruction fetch
DLX_bus_monitor: Command I-fetch from X"00000010", word
DLX_bus_monitor: Ready, instruction X"1440FFF8" [ BNEZ     R2, -8 ]
controller: decode, reg-read and PC incr
s2_monitor: X"00000004"
dest_monitor: X"00000000"
dest_monitor: X"00000004"
s1_monitor: X"00000010"
dest_monitor: X"00000014"
s2_monitor: X"00000000"
s1_monitor: X"00000000"
controller: execute
dest_monitor: X"00000000"
s1_monitor: X"00000009"
dest_monitor: X"00000009"
s1_monitor: X"00000000"
controller: memory access or branch completion
dest_monitor: X"00000000"
s2_monitor: X"FFFFFFF8"
s1_monitor: X"00000014"
dest_monitor: X"0000000C"
s2_monitor: X"00000000"
s1_monitor: X"00000000"
controller: write-back
controller: instruction fetch
DLX_bus_monitor: Command I-fetch from X"0000000C", word
DLX_bus_monitor: Ready, instruction X"2C420001" [ SUBUI    R2, R2, 1 ]
controller: decode, reg-read and PC incr
s2_monitor: X"00000004"
dest_monitor: X"00000000"
dest_monitor: X"00000004"
s1_monitor: X"0000000C"
dest_monitor: X"00000010"
s2_monitor: X"00000000"
s1_monitor: X"00000000"
controller: execute
dest_monitor: X"00000000"
s2_monitor: X"00000001"
s1_monitor: X"00000009"
dest_monitor: X"00000008"
s2_monitor: X"00000000"
s1_monitor: X"00000000"
controller: memory access or branch completion
controller: write-back
controller: instruction fetch
DLX_bus_monitor: Command I-fetch from X"00000010", word
DLX_bus_monitor: Ready, instruction X"1440FFF8" [ BNEZ     R2, -8 ]
controller: decode, reg-read and PC incr
s2_monitor: X"00000004"
dest_monitor: X"00000000"
dest_monitor: X"00000004"
s1_monitor: X"00000010"
dest_monitor: X"00000014"
s2_monitor: X"00000000"
s1_monitor: X"00000000"
controller: execute
dest_monitor: X"00000000"
s1_monitor: X"00000008"
dest_monitor: X"00000008"
s1_monitor: X"00000000"
controller: memory access or branch completion
dest_monitor: X"00000000"
s2_monitor: X"FFFFFFF8"
s1_monitor: X"00000014"
dest_monitor: X"0000000C"
s2_monitor: X"00000000"
s1_monitor: X"00000000"
controller: write-back
controller: instruction fetch
DLX_bus_monitor: Command I-fetch from X"0000000C", word
DLX_bus_monitor: Ready, instruction X"2C420001" [ SUBUI    R2, R2, 1 ]
controller: decode, reg-read and PC incr
s2_monitor: X"00000004"
dest_monitor: X"00000000"
dest_monitor: X"00000004"
s1_monitor: X"0000000C"
dest_monitor: X"00000010"
s2_monitor: X"00000000"
s1_monitor: X"00000000"
controller: execute
dest_monitor: X"00000000"
s2_monitor: X"00000001"
s1_monitor: X"00000008"
dest_monitor: X"00000007"
s2_monitor: X"00000000"
s1_monitor: X"00000000"
controller: memory access or branch completion
controller: write-back
controller: instruction fetch
DLX_bus_monitor: Command I-fetch from X"00000010", word
DLX_bus_monitor: Ready, instruction X"1440FFF8" [ BNEZ     R2, -8 ]
controller: decode, reg-read and PC incr
s2_monitor: X"00000004"
dest_monitor: X"00000000"
dest_monitor: X"00000004"
s1_monitor: X"00000010"
dest_monitor: X"00000014"
s2_monitor: X"00000000"
s1_monitor: X"00000000"
controller: execute
dest_monitor: X"00000000"
s1_monitor: X"00000007"
dest_monitor: X"00000007"
s1_monitor: X"00000000"
controller: memory access or branch completion
dest_monitor: X"00000000"
s2_monitor: X"FFFFFFF8"
s1_monitor: X"00000014"
dest_monitor: X"0000000C"
s2_monitor: X"00000000"
s1_monitor: X"00000000"
controller: write-back
controller: instruction fetch
DLX_bus_monitor: Command I-fetch from X"0000000C", word
DLX_bus_monitor: Ready, instruction X"2C420001" [ SUBUI    R2, R2, 1 ]
controller: decode, reg-read and PC incr
s2_monitor: X"00000004"
dest_monitor: X"00000000"
dest_monitor: X"00000004"
s1_monitor: X"0000000C"
dest_monitor: X"00000010"
s2_monitor: X"00000000"
s1_monitor: X"00000000"
controller: execute
dest_monitor: X"00000000"
s2_monitor: X"00000001"
s1_monitor: X"00000007"
dest_monitor: X"00000006"
s2_monitor: X"00000000"
s1_monitor: X"00000000"
controller: memory access or branch completion
controller: write-back
controller: instruction fetch
DLX_bus_monitor: Command I-fetch from X"00000010", word
DLX_bus_monitor: Ready, instruction X"1440FFF8" [ BNEZ     R2, -8 ]
controller: decode, reg-read and PC incr
s2_monitor: X"00000004"
dest_monitor: X"00000000"
dest_monitor: X"00000004"
s1_monitor: X"00000010"
dest_monitor: X"00000014"
s2_monitor: X"00000000"
s1_monitor: X"00000000"
controller: execute
dest_monitor: X"00000000"
s1_monitor: X"00000006"
dest_monitor: X"00000006"
s1_monitor: X"00000000"
controller: memory access or branch completion
dest_monitor: X"00000000"
s2_monitor: X"FFFFFFF8"
s1_monitor: X"00000014"
dest_monitor: X"0000000C"
s2_monitor: X"00000000"
s1_monitor: X"00000000"
controller: write-back
controller: instruction fetch
DLX_bus_monitor: Command I-fetch from X"0000000C", word
DLX_bus_monitor: Ready, instruction X"2C420001" [ SUBUI    R2, R2, 1 ]
controller: decode, reg-read and PC incr
s2_monitor: X"00000004"
dest_monitor: X"00000000"
dest_monitor: X"00000004"
s1_monitor: X"0000000C"
dest_monitor: X"00000010"
s2_monitor: X"00000000"
s1_monitor: X"00000000"
controller: execute
dest_monitor: X"00000000"
s2_monitor: X"00000001"
s1_monitor: X"00000006"
dest_monitor: X"00000005"
s2_monitor: X"00000000"
s1_monitor: X"00000000"
controller: memory access or branch completion
controller: write-back
controller: instruction fetch
DLX_bus_monitor: Command I-fetch from X"00000010", word
DLX_bus_monitor: Ready, instruction X"1440FFF8" [ BNEZ     R2, -8 ]
controller: decode, reg-read and PC incr
s2_monitor: X"00000004"
dest_monitor: X"00000000"
dest_monitor: X"00000004"
s1_monitor: X"00000010"
dest_monitor: X"00000014"
s2_monitor: X"00000000"
s1_monitor: X"00000000"
controller: execute
dest_monitor: X"00000000"
s1_monitor: X"00000005"
dest_monitor: X"00000005"
s1_monitor: X"00000000"
controller: memory access or branch completion
dest_monitor: X"00000000"
s2_monitor: X"FFFFFFF8"
s1_monitor: X"00000014"
dest_monitor: X"0000000C"
s2_monitor: X"00000000"
s1_monitor: X"00000000"
controller: write-back
controller: instruction fetch
DLX_bus_monitor: Command I-fetch from X"0000000C", word
DLX_bus_monitor: Ready, instruction X"2C420001" [ SUBUI    R2, R2, 1 ]
controller: decode, reg-read and PC incr
s2_monitor: X"00000004"
dest_monitor: X"00000000"
dest_monitor: X"00000004"
s1_monitor: X"0000000C"
dest_monitor: X"00000010"
s2_monitor: X"00000000"
s1_monitor: X"00000000"
controller: execute
dest_monitor: X"00000000"
s2_monitor: X"00000001"
s1_monitor: X"00000005"
dest_monitor: X"00000004"
s2_monitor: X"00000000"
s1_monitor: X"00000000"
controller: memory access or branch completion
controller: write-back
controller: instruction fetch
DLX_bus_monitor: Command I-fetch from X"00000010", word
DLX_bus_monitor: Ready, instruction X"1440FFF8" [ BNEZ     R2, -8 ]
controller: decode, reg-read and PC incr
s2_monitor: X"00000004"
dest_monitor: X"00000000"
dest_monitor: X"00000004"
s1_monitor: X"00000010"
dest_monitor: X"00000014"
s2_monitor: X"00000000"
s1_monitor: X"00000000"
controller: execute
dest_monitor: X"00000000"
s1_monitor: X"00000004"
dest_monitor: X"00000004"
s1_monitor: X"00000000"
controller: memory access or branch completion
dest_monitor: X"00000000"
s2_monitor: X"FFFFFFF8"
s1_monitor: X"00000014"
dest_monitor: X"0000000C"
s2_monitor: X"00000000"
s1_monitor: X"00000000"
controller: write-back
controller: instruction fetch
DLX_bus_monitor: Command I-fetch from X"0000000C", word
DLX_bus_monitor: Ready, instruction X"2C420001" [ SUBUI    R2, R2, 1 ]
controller: decode, reg-read and PC incr
s2_monitor: X"00000004"
dest_monitor: X"00000000"
dest_monitor: X"00000004"
s1_monitor: X"0000000C"
dest_monitor: X"00000010"
s2_monitor: X"00000000"
s1_monitor: X"00000000"
controller: execute
dest_monitor: X"00000000"
s2_monitor: X"00000001"
s1_monitor: X"00000004"
dest_monitor: X"00000003"
s2_monitor: X"00000000"
s1_monitor: X"00000000"
controller: memory access or branch completion
controller: write-back
controller: instruction fetch
DLX_bus_monitor: Command I-fetch from X"00000010", word
DLX_bus_monitor: Ready, instruction X"1440FFF8" [ BNEZ     R2, -8 ]
controller: decode, reg-read and PC incr
s2_monitor: X"00000004"
dest_monitor: X"00000000"
dest_monitor: X"00000004"
s1_monitor: X"00000010"
dest_monitor: X"00000014"
s2_monitor: X"00000000"
s1_monitor: X"00000000"
controller: execute
dest_monitor: X"00000000"
s1_monitor: X"00000003"
dest_monitor: X"00000003"
s1_monitor: X"00000000"
controller: memory access or branch completion
dest_monitor: X"00000000"
s2_monitor: X"FFFFFFF8"
s1_monitor: X"00000014"
dest_monitor: X"0000000C"
s2_monitor: X"00000000"
s1_monitor: X"00000000"
controller: write-back
controller: instruction fetch
DLX_bus_monitor: Command I-fetch from X"0000000C", word
DLX_bus_monitor: Ready, instruction X"2C420001" [ SUBUI    R2, R2, 1 ]
controller: decode, reg-read and PC incr
s2_monitor: X"00000004"
dest_monitor: X"00000000"
dest_monitor: X"00000004"
s1_monitor: X"0000000C"
dest_monitor: X"00000010"
s2_monitor: X"00000000"
s1_monitor: X"00000000"
controller: execute
dest_monitor: X"00000000"
s2_monitor: X"00000001"
s1_monitor: X"00000003"
dest_monitor: X"00000002"
s2_monitor: X"00000000"
s1_monitor: X"00000000"
controller: memory access or branch completion
controller: write-back
controller: instruction fetch
DLX_bus_monitor: Command I-fetch from X"00000010", word
DLX_bus_monitor: Ready, instruction X"1440FFF8" [ BNEZ     R2, -8 ]
controller: decode, reg-read and PC incr
s2_monitor: X"00000004"
dest_monitor: X"00000000"
dest_monitor: X"00000004"
s1_monitor: X"00000010"
dest_monitor: X"00000014"
s2_monitor: X"00000000"
s1_monitor: X"00000000"
controller: execute
dest_monitor: X"00000000"
s1_monitor: X"00000002"
dest_monitor: X"00000002"
s1_monitor: X"00000000"
controller: memory access or branch completion
dest_monitor: X"00000000"
s2_monitor: X"FFFFFFF8"
s1_monitor: X"00000014"
dest_monitor: X"0000000C"
s2_monitor: X"00000000"
s1_monitor: X"00000000"
controller: write-back
controller: instruction fetch
DLX_bus_monitor: Command I-fetch from X"0000000C", word
DLX_bus_monitor: Ready, instruction X"2C420001" [ SUBUI    R2, R2, 1 ]
controller: decode, reg-read and PC incr
s2_monitor: X"00000004"
dest_monitor: X"00000000"
dest_monitor: X"00000004"
s1_monitor: X"0000000C"
dest_monitor: X"00000010"
s2_monitor: X"00000000"
s1_monitor: X"00000000"
controller: execute
dest_monitor: X"00000000"
s2_monitor: X"00000001"
s1_monitor: X"00000002"
dest_monitor: X"00000001"
s2_monitor: X"00000000"
s1_monitor: X"00000000"
controller: memory access or branch completion
controller: write-back
controller: instruction fetch
DLX_bus_monitor: Command I-fetch from X"00000010", word
DLX_bus_monitor: Ready, instruction X"1440FFF8" [ BNEZ     R2, -8 ]
controller: decode, reg-read and PC incr
s2_monitor: X"00000004"
dest_monitor: X"00000000"
dest_monitor: X"00000004"
s1_monitor: X"00000010"
dest_monitor: X"00000014"
s2_monitor: X"00000000"
s1_monitor: X"00000000"
controller: execute
dest_monitor: X"00000000"
s1_monitor: X"00000001"
dest_monitor: X"00000001"
s1_monitor: X"00000000"
controller: memory access or branch completion
dest_monitor: X"00000000"
s2_monitor: X"FFFFFFF8"
s1_monitor: X"00000014"
dest_monitor: X"0000000C"
s2_monitor: X"00000000"
s1_monitor: X"00000000"
controller: write-back
controller: instruction fetch
DLX_bus_monitor: Command I-fetch from X"0000000C", word
DLX_bus_monitor: Ready, instruction X"2C420001" [ SUBUI    R2, R2, 1 ]
controller: decode, reg-read and PC incr
s2_monitor: X"00000004"
dest_monitor: X"00000000"
dest_monitor: X"00000004"
s1_monitor: X"0000000C"
dest_monitor: X"00000010"
s2_monitor: X"00000000"
s1_monitor: X"00000000"
controller: execute
dest_monitor: X"00000000"
s2_monitor: X"00000001"
s1_monitor: X"00000001"
s2_monitor: X"00000000"
s1_monitor: X"00000000"
controller: memory access or branch completion
controller: write-back
controller: instruction fetch
DLX_bus_monitor: Command I-fetch from X"00000010", word
DLX_bus_monitor: Ready, instruction X"1440FFF8" [ BNEZ     R2, -8 ]
controller: decode, reg-read and PC incr
s2_monitor: X"00000004"
dest_monitor: X"00000004"
s1_monitor: X"00000010"
dest_monitor: X"00000014"
s2_monitor: X"00000000"
s1_monitor: X"00000000"
controller: execute
dest_monitor: X"00000000"
controller: memory access or branch completion
controller: write-back
controller: instruction fetch
DLX_bus_monitor: Command I-fetch from X"00000014", word
DLX_bus_monitor: Ready, instruction X"8C010028" [ LW       R1, 40(R0) ]
controller: decode, reg-read and PC incr
s2_monitor: X"00000004"
dest_monitor: X"00000004"
s1_monitor: X"00000014"
dest_monitor: X"00000018"
s2_monitor: X"00000000"
s1_monitor: X"00000000"
controller: execute
dest_monitor: X"00000000"
s2_monitor: X"00000028"
dest_monitor: X"00000028"
s2_monitor: X"00000000"
controller: memory access or branch completion
DLX_bus_monitor: Command D-read from X"00000028", word
DLX_bus_monitor: Ready, data X"00000001"
dest_monitor: X"00000000"
s1_monitor: X"00000001"
dest_monitor: X"00000001"
s1_monitor: X"00000000"
controller: write-back
controller: instruction fetch
DLX_bus_monitor: Command I-fetch from X"00000018", word
DLX_bus_monitor: Ready, instruction X"2C210001" [ SUBUI    R1, R1, 1 ]
controller: decode, reg-read and PC incr
s2_monitor: X"00000004"
dest_monitor: X"00000000"
dest_monitor: X"00000004"
s1_monitor: X"00000018"
dest_monitor: X"0000001C"
s2_monitor: X"00000000"
s1_monitor: X"00000000"
controller: execute
dest_monitor: X"00000000"
s2_monitor: X"00000001"
s1_monitor: X"00000001"
s2_monitor: X"00000000"
s1_monitor: X"00000000"
controller: memory access or branch completion
controller: write-back
controller: instruction fetch
DLX_bus_monitor: Command I-fetch from X"0000001C", word
DLX_bus_monitor: Ready, instruction X"AC010028" [ SW       40(R0), R1 ]
controller: decode, reg-read and PC incr
s2_monitor: X"00000004"
dest_monitor: X"00000004"
s1_monitor: X"0000001C"
dest_monitor: X"00000020"
s2_monitor: X"00000000"
s1_monitor: X"00000000"
controller: execute
dest_monitor: X"00000000"
s2_monitor: X"00000028"
dest_monitor: X"00000028"
s2_monitor: X"00000000"
controller: memory access or branch completion
dest_monitor: X"00000000"
DLX_bus_monitor: Command D-write to X"00000028", word, data X"00000000"
DLX_bus_monitor: Ready
controller: write-back
controller: instruction fetch
DLX_bus_monitor: Command I-fetch from X"00000020", word
DLX_bus_monitor: Ready, instruction X"1420FFE4" [ BNEZ     R1, -28 ]
controller: decode, reg-read and PC incr
s2_monitor: X"00000004"
dest_monitor: X"00000004"
s1_monitor: X"00000020"
dest_monitor: X"00000024"
s2_monitor: X"00000000"
s1_monitor: X"00000000"
controller: execute
dest_monitor: X"00000000"
controller: memory access or branch completion
controller: write-back
controller: instruction fetch
DLX_bus_monitor: Command I-fetch from X"00000024", word
DLX_bus_monitor: Ready, instruction X"44000000" [ TRAP     0 ]
controller: decode, reg-read and PC incr
s2_monitor: X"00000004"
dest_monitor: X"00000004"
s1_monitor: X"00000024"
dest_monitor: X"00000028"
s2_monitor: X"00000000"
s1_monitor: X"00000000"
controller: execute
               Assertion Violation: at time = 5400000000 fs + 2,
                 in process /dlx_test(bench).the_controller,
                 from line 1662 of file /a/eeyore/chamlang/users/cs/petera/vsim/benchmarks/dlx/dlx_test_bench.vhdl,
                 Note: "TRAP instruction encountered, execution halted".