RISC versus CISC pipelines
Pipelines for CISC are required to handle complex memory to register addressing
- mov r4, (r3, r2)4 <= EA is r3 + r2 + 4
- Will have an extra stage for Effective address calculation (see Figures 5.40, 5.41, 5.43)
- Some CISC pipelines avoid a load-use delay penalty (Fig 5.54, 5.56)
RISC pipelines have a load-use penalty of at least one
Determining load-use penalties when multiple pipelines are in action are instruction sequence dependent (ie., 1, 2, more than 2 cycles)