;**************************************************************************** ; ; Generated cadence technology file ; ; Script: tech.perl ; Arguments: 0.3 ../drSCMOS.perl ../../scn06hp/prm/generalExtract.perl ../../scn06hp/base/padDefGdt.perl addMET3 addSILBLK addCWELL ; Date: Tue Aug 4 12:51:39 CDT 1998 ; ;**************************************************************************** controls( techParams((lambda 0.3)) ) layerDefinitions( techPurposes( ;( PurposeName Purpose# Abbreviation ) ;( ----------- -------- ------------ ) ;User-Defined Purposes: ( bond 100 bnd ) ( drawingn 101 drn ) ( drawingp 102 drp ) ( cut 103 cut ) ( mask 104 msk ) ) ;techPurposes techLayers( ;( LayerName Layer# Abbreviation ) ;( --------- ------ ------------ ) ;User-Defined Layers: ( nwell 1 nwell ) ( diff 2 diff ) ( difftap 3 difftap ) ( ndiff 4 ndiff ) ( pdiff 5 pdiff ) ( pactive 6 pactive ) ( nactive 7 nactive ) ( tap 8 tap ) ( poly 9 poly ) ( mcon 11 mcon ) ( met1 12 met1 ) ( via 13 via ) ( met2 14 met2 ) ( via2 15 via2 ) ( met3 16 met3 ) ( glass 19 glass ) ( cwell 22 cwell ) ( silblk 23 silblk ) ( nselect 24 nselect ) ( pselect 25 pselect ) ( areaid 26 areaid ) ; These next layers are added for backward contact compatability ( pcon 27 pcon ) ( acon 28 acon ) ); techLayers techLayerPurposePriorities( ;layers are ordered from lowest to highest priority ;( LayerName Purpose ) ;( --------- ------- ) ( nwell drawing ) ( nwell pin ) ( nwell net ) ( nwell mask ) ( cwell drawing ) ( cwell pin ) ( cwell net ) ( cwell mask ) ( diff drawing ) ( diff pin ) ( diff net ) ( tap drawing ) ( tap pin ) ( tap net ) ( difftap mask ) ( pdiff drawing ) ( pdiff net ) ( ndiff drawing ) ( ndiff net ) ( pactive drawing ) ( nactive drawing ) ( poly drawing ) ( poly pin ) ( poly net ) ( poly mask ) ( silblk drawing ) ( silblk mask ) ( mcon drawing ) ( mcon pin ) ( mcon net ) ( mcon mask ) ( pcon mask ) ( acon mask ) ( met1 drawing ) ( met1 pin ) ( met1 net ) ( met1 mask ) ( via drawing ) ( via pin ) ( via net ) ( via mask ) ( met2 drawing ) ( met2 pin ) ( met2 net ) ( met2 mask ) ( via2 drawing ) ( via2 pin ) ( via2 net ) ( via2 mask ) ( met3 drawing ) ( met3 pin ) ( met3 net ) ( met3 mask ) ( nselect drawing ) ( nselect mask ) ( pselect drawing ) ( pselect mask ) ( glass drawing ) ( glass mask ) ( areaid bond ) ) ;techLayerPurposePriorities techDisplays( ;( LayerName Purpose Packet Vis Sel Con2ChgLy DrgEnbl Valid ) ;( --------- ------- ------ --- --- --------- ------- ----- ) ( nwell drawing nwelldr t t t t t ) ( nwell pin nwellmk t t nil t nil ) ( nwell net nwelldr t t nil t nil ) ( nwell mask nwellmk t t nil t nil ) ( diff drawing diffdr t t t t t ) ( diff pin diffdr t t t t t ) ( diff net diffdr t t nil t nil ) ( pdiff drawing tapdr t t nil t nil ) ( pactive drawing tapdr t t nil t nil ) ( pdiff net tapdr t t nil t nil ) ( ndiff drawing diffdr t t nil t nil ) ( nactive drawing diffdr t t nil t nil ) ( ndiff net diffdr t t nil t nil ) ( tap drawing tapdr t t t t t ) ( tap pin tapdr t t t t t ) ( tap net tapdr t t nil t nil ) ( difftap mask difftapmk t t nil t nil ) ( poly drawing polydr t t t t t ) ( poly pin polymk t t t t t ) ( poly net polydr t t nil t nil ) ( poly mask polymk t t nil t nil ) ( mcon drawing mcondr t t t t t ) ( mcon pin mconmk t t nil t nil ) ( mcon net mcondr t t nil t nil ) ( mcon mask mconmk t t nil t nil ) ( pcon mask mconmk t t nil t nil ) ( acon mask mconmk t t nil t nil ) ( met1 drawing met1dr t t t t t ) ( met1 pin met1mk t t t t t ) ( met1 net met1dr t t nil t nil ) ( met1 mask met1mk t t nil t nil ) ( via drawing viadr t t t t t ) ( via pin viamk t t nil t nil ) ( via net viadr t t nil t nil ) ( via mask viamk t t nil t nil ) ( met2 drawing met2dr t t t t t ) ( met2 pin met2mk t t t t t ) ( met2 net met2dr t t nil t nil ) ( met2 mask met2mk t t nil t nil ) ( nselect drawing nselectdr t t nil t nil ) ( nselect mask nselectmk t t nil t nil ) ( pselect drawing pselectdr t t nil t nil ) ( pselect mask pselectmk t t nil t nil ) ( glass drawing glassdr t t t t t ) ( glass mask glassmk t t nil t nil ) ( areaid bond areaidbd t t nil t nil ) ( via2 drawing via2dr t t t t t ) ( via2 pin via2mk t t nil t nil ) ( via2 net via2dr t t nil t nil ) ( via2 mask via2mk t t nil t nil ) ( met3 drawing met3dr t t t t t ) ( met3 pin met3mk t t t t t ) ( met3 net met2dr t t nil t nil ) ( met3 mask met3mk t t nil t nil ) ( silblk drawing silblkdr t t t t t ) ( silblk mask silblkmk t t nil t nil ) ( cwell drawing cwelldr t t t t t ) ( cwell pin cwellmk t t nil t nil ) ( cwell net cwelldr t t nil t nil ) ( cwell mask cwellmk t t nil t nil ) ) ;techDisplays ) ;LayerDefinitions layerRules( viaLayers( ;( layer1 viaLayer layer2 ) ;( ------ -------- ------ ) ( poly mcon met1 ) ( met1 via met2 ) ( met2 via2 met3 ) ) ;viaLayers streamLayers( ;( layer streamNumber dataType translate ) ;( ----- ------------ -------- --------- ) ( ( "nwell" "mask" ) 42 0 t ) ( ( "difftap" "mask") 43 0 t ) ( ( "poly" "mask" ) 46 0 t ) ( ( "mcon" "mask" ) 25 0 t ) ( ( "pcon" "mask" ) 47 0 t ) ( ( "acon" "mask" ) 48 0 t ) ( ( "met1" "mask" ) 49 0 t ) ( ( "via" "mask" ) 50 0 t ) ( ( "met2" "mask" ) 51 0 t ) ( ( "glass" "mask" ) 52 0 t ) ( ( "areaid" "bond" ) 26 0 t ) ( ( "pselect" "mask") 44 0 t ) ( ( "nselect" "mask") 45 0 t ) ( ( "via2" "mask" ) 61 0 t ) ( ( "met3" "mask" ) 62 0 t ) ( ( "silblk" "mask" ) 29 0 t ) ( ( "cwell" "mask" ) 59 0 t ) ) ;streamLayers );layerRules ;********************************* ; SYMBOLIC DEVICES ;********************************* ; The declaration of symbolic wires are not in the "device" class. It has been ; replaced with "symWire" sub-class in the compactorRules class. devices( tcCreateCDSDeviceClass() ; symEnhancementDevice( ;(name sdLayer sdPurpose gateLayer gatePurpose w l sdExt gateExt legalRegion) ; (PTR diff drawing (pimplant drawing .3) poly drawing 1.8 .6 1.2 .9 ; (outside pwell drawing)) ; (NTR diff drawing poly drawing 1.8 .6 1.2 .9 (inside pwell drawing)) ; ) symEnhancementDevice( ;(name sdLayer sdPurpose gateLayer gatePurpose w l sdExt gateExt legalRegion) (PTR diff drawing poly drawing .9 .6 .9 .6 (inside nwell drawing)) (NTR diff drawing poly drawing .9 .6 .9 .6 (outside nwell drawing)) ) symContactDevice( ; viaName viaLayer viaPurpose layer1 purpose1 layer2 purpose2 ; ------- -------- ---------- ------ -------- ------ -------- ; w l (row column xPitch yPitch xBias yBias) encL1 encL2 legalRegion ; - - --- ------ ------ ------ ----- ----- ----- ----- ----------- ; tieHigh/low to GE/C3 mastersliceLayers ( M1_P mcon drawing pdiff drawing met1 drawing .6 .6 ( 1 1 1.2 1.2 center center) .3 .3 _NA_ ) ( M1_N mcon drawing ndiff drawing met1 drawing .6 .6 ( 1 1 1.2 1.2 center center) .3 .3 _NA_ ) ( M1_POLY mcon drawing poly drawing met1 drawing .6 .6 ( 1 1 1.2 1.2 center center) .3 .3 _NA_ ) ; for full route segment via/contact ( M2_M1 via drawing met1 drawing met2 drawing .6 .6 ( 1 1 1.2 1.2 center center) .3 .3 _NA_ ) ( M3_M2 via2 drawing met2 drawing met3 drawing .6 .6 ( 1 1 1.8 1.8 center center) .6 .6 _NA_ ) ) ; end symContactDevice ruleContactDevice( ( ruleVia ( met1 drawing ( -0.600000 -0.600000 0.600000 0.600000 ) ) ( via drawing ( -0.300000 -0.300000 0.300000 0.300000 ) ) ( met2 drawing ( -0.600000 -0.600000 0.600000 0.600000 ) ) ) ) ; end ruleContactDevice symPinDevice( ; nonMaskable symbolic pins to represent softPins on softBlocks (for Preview) ; (name maskable layer1 purpose1 w1 layer2 purpose2 w2 legalRegion) (poly_T nil poly drawing .6 _NA_ _NA_ _NA_ _NA_) (met1_T nil met1 drawing .6 _NA_ _NA_ _NA_ _NA_) (met2_T nil met2 drawing .6 _NA_ _NA_ _NA_ _NA_) ; 2-layer softPins to leave the routeLayer assignment to the routers. (met12_T nil met1 drawing .6 met2 drawing .6 _NA_) (met23_T nil met2 drawing .6 met3 drawing .6 _NA_) (met13_T nil met1 drawing .6 met3 drawing .6 _NA_) ) ); end of symbolic devices physicalRules( orderedSpacingRules( ; order dependent ; ; layer1 encloses layer2 ;( rule layer1 layer2 value ) ( minEnclosure nwell diff 1.8 ) ( minEnclosure nwell tap 0.9 ) ( minEnclosure poly diff 0.6 ) ( minEnclosure diff poly 0.9 ) ( minEnclosure poly mcon 0.3 ) ( minEnclosure diff mcon 0.3 ) ( minEnclosure tap mcon 0.3 ) ( minEnclosure met1 mcon 0.3 ) ( minEnclosure met1 via 0.3 ) ( minEnclosure met2 via 0.3 ) ( minEnclosure met2 via2 0.3 ) ( minEnclosure met3 via2 0.6 ) ( minEnclosure cwell tap 0.9 ) ) ;orderedSpacingRules spacingRules( ;( rule layer1 layer2 value ) ; nwell ( minWidth nwell 3.0 ) ; don't know how to check for diff potential well ( minSpacing nwell 1.8 ) ( minNotch nwell 1.8 ) ; active ( minWidth diff 0.9 ) ( minWidth tap 0.9 ) ( minSpacing diff 0.9 ) ( minNotch diff 0.9 ) ( minSpacing tap 0.9 ) ( minNotch tap 0.9 ) ( minSpacing diff nwell 1.8 ) ( minSpacing tap nwell 0.9 ) ( minSpacing diff tap 1.2 ) ; poly ( minWidth poly 0.6 ) ( minSpacing poly 0.6 ) ( minNotch poly 0.6 ) ( minSpacing poly diff 0.3 ) ( minSpacing poly tap 0.3 ) ; select ; need select rules ; mcon ; using 5 for all mcon ( minWidth mcon 0.6 ) ( maxWidth mcon 0.6 ) ( minSpacing mcon 0.6 ) ; need channel definition for 5.4 ; need 5.5b ; need 5.6b ; need 5.7b ; need 6.5b ; need 6.6b ; need 6.7b ; need 6.8b ; met1 ; need to fix for tightmetal ( minWidth met1 0.9 ) ( minSpacing met1 0.9 ) ( minNotch met1 0.9 ) ; via ( minWidth via 0.6 ) ( maxWidth via 0.6 ) ( minSpacing via 0.9 ) ( minSpacing via mcon 0.6 ) ( minSpacing via poly 0.6 ) ( minSpacing via diff 0.6 ) ( minSpacing via tap 0.6 ) ; met2 ; need to fix for tightmetal ( minWidth met2 0.9 ) ( minSpacing met2 1.2 ) ( minNotch met2 1.2 ) ; glass ; need to add glass and pad rules ; via2 ( minWidth via2 0.6 ) ( maxWidth via2 0.6 ) ( minSpacing via2 0.9 ) ( minSpacing via2 via 0.6 ) ; met3 ( minWidth met3 1.8 ) ( minSpacing met3 1.2 ) ( minNotch met3 1.2 ) ; cwell ( minWidth cwell 3.0 ) ( minSpacing cwell 2.7 ) ( minNotch cwell 2.7 ) ( minSpacing cwell diff 1.5 ) ( minSpacing cwell tap 1.5 ) ; need to add rules for the linear cap here (18) ; silblk ( minWidth silblk 1.2 ) ( minSpacing silblk 1.2 ) ( minNotch silblk 1.2 ) ( minSpacing silblk mcon 0.6 ) ( minSpacing silblk diff 0.6 ) ( minSpacing silblk tap 0.6 ) ( minSpacing silblk poly 0.6 ) ; need to add resistor rules 20.6 20.7 20.8 20.9 ) ;spacingRules mfgGridResolution( ( 0.100000 ) ) ;mfgGridResolution ) ;physicalRules electricalRules( characterizationRules( ;( rule layer value ) ; poly ( areaCap poly 87.0e-4 ) ( edgeCapacitance poly 4.0e-11 ) ( sheetRes poly 2.6 ) ( parallelCap poly met1 58.0e-4 ) ( parallelCap poly met2 13.0e-4 ) ( parallelCap diff poly 3585.0e-4 ) ( parallelCap tap poly 3585.0e-4 ) ; met1 ( areaCap met1 36.0e-4 ) ( edgeCapacitance met1 86.0e-4 ) ( sheetRes met1 0.08 ) ( parallelCap met1 met2 31.0e-4 ) ( parallelCap diff met1 59.0e-4 ) ( parallelCap tap met1 59.0e-4 ) ; met2 ( areaCap met2 11.0e-4 ) ( edgeCapacitance met2 77.0e-4 ) ( sheetRes met2 0.07 ) ( parallelCap diff met2 15.0e-4 ) ( parallelCap tap met2 15.0e-4 ) ; via ( sheetRes via 0.61 ) ; mcon ( sheetRes mcon 2.6 ) ; met3 ( areaCap met3 7.0e-4 ) ( edgeCapacitance met3 31.0e-4 ) ( sheetRes met3 0.03 ) ( parallelCap poly met3 8.0e-4 ) ( parallelCap met1 met3 10.0e-4 ) ( parallelCap met2 met3 28.0e-4 ) ( parallelCap diff met3 7.0e-4 ) ( parallelCap tap met3 7.0e-4 ) ; via2 ( sheetRes via2 0.62 ) ) ;characterizationRules ) ;electricalRules prRules( prRoutingLayers( ;( layer preferredDirection ) ( met1 "horizontal" ) ( met2 "vertical" ) ( met3 "horizontal" ) ) ;prRoutingLayers prViaTypes( ;( device cellViewName viaType ) ;( ------------------------ ------- ) ( ( "M2_M1" "symbolic" ) "default" ) ( ( "M3_M2" "symbolic" ) "default" ) ) ;prViaTypes prRoutingPitch( ;( layer pitch ) ( met1 2.4 ) ( met2 2.4 ) ( met3 3.6 ) ) ;prRoutingPitch prRoutingOffset( ;( layer offset ) ( met1 0.0 ) ( met2 0.0 ) ( met3 0.0 ) ) ;prRoutingOffset prOverlapLayer( prBoundary ) ;prOverlapLayer ; optional for GE / C3 prMastersliceLayers( ; layers : listed in order of lowest (closest to substrate) to highest ( ndiff pdiff poly ) ) prGenViaRules( ; for GE/C3 SROUTE or Preview's PowerRoute (for GE/C3) ; viaRuleName definition is order-sensitive ; viaRuleName viaLayer ( w l xPitch yPitch resistance) ; ----------- -------- - - ------ ------ ---------- ; layer1 direction (wMin wMax overhang metalOverHang) ; ------ --------- ---------------------------------- ; layer2 direction (wMin wMax overhang metalOverhang) ; ------ --------- ---------------------------------- (viagen21 via ( 0.6 0.6 1.2 1.2 0.001 ) ;R per cut optional met1 "horizontal" ( 1.2 120.0 0.3 0.0 ) met2 "vertical" ( 1.2 120.0 0.3 0.0 ) ) (viagen32 via2 ( 0.6 0.6 1.2 1.2 0.001 ) ; use default met2 "vertical" ( 1.2 120.0 0.3 0.0 ) met3 "horizontal" ( 1.8 180.0 0.6 0.0 ) ) ) prTurnViaRules( ;( turnViaRuleName layer (directionList) ) ( "TURN1" met1 ("vertical" "horizontal") ) ( "TURN2" met2 ("vertical" "horizontal") ) ( "TURN3" met3 ("vertical" "horizontal") ) ) ;prTurnViaRules ) ;prRules ;;; still need to add las rules, compactor rules, dle rules, dlr rules ;;; and le rules