MPL VHDL Model Collection

All Libraries

Note: The following is a complete alphabetized listing of all the libraries.

Downloaded Archives

   cypress

   cypress.cy7b134

1.1 

  RAM:  4K x 8 Dual Port SRAM
        w/ OE, CE, R/W, non-separate I/O, 
        and semaphores

   cypress.cy7b138

1.1 

  RAM:  4K x 8 Dual Port SRAM
        w/ OE, CE, R/W, non-separate I/O, 
        Int, Busy, and Semaphores

   cypress.cy7b195

1.2 

  RAM:  64K x 4 BiCMOS SRAM
        w/ CE, OE, WE, and non-separate I/O

   cypress.cy7b199

1.2 

  RAM:  32K x 8 SRAM
        w/ CE, OE, WE, and non-separate I/O

   cypress.cy7c1006

1.1 

  RAM:  256K x 4 SRAM
        w/ CE, OE, WE, and non-separate I/O

   cypress.cy7c1007

1.1 

  RAM:  1M x 1 SRAM
        w/ CE, WE, and separate I/O

   cypress.cy7c195

1.2 

  RAM:  64K x 4 SRAM
        w/ CE, OE, WE, and non-separate I/O

   cypress.cy7c199

1.2 

  RAM:  32K x 8 SRAM
        w/ CE, WE, OE, and non-separate I/O

   cypress.cy7c256

1.2 

  PROM:  32K x 8 PROM
        w/ CE and OE, Switched and 
        Reprogrammable

   cypress.cy7c266

1.1 

  PROM:  8K x 8 PROM
        w/ OE and CE, Switched and 
        Reprogrammable

   cypress.cy7c276

1.1 

  PROM:  16K x 16 PROM
        w/ CS0, CS1, CS2, and OE; 
        Reprogrammable

   cypress.cy7c285

1.2 

  PROM:  64K x 8 PROM
        w/ CS; Reprogrammable Fast 
        Column Access

   cypress.cy7c401

1.1 

  FIFO:  64 x 4 FIFO
        w/ MR, OE, SI, and SO; Cascadable

   cypress.cy7c402

1.1 

  FIFO:  64 x 5 FIFO 
        w/ MR, OE, SI, and SO; Cascadable

   cypress.cy7c403

1.1 

  FIFO:  64 x 4 FIFO
        w/ MR, OE, SI, and SO; Cascadable

   cypress.cy7c404

1.1 

  FIFO:  64 x 5 FIFO
        w/ MR, OE, SI, and SO; Cascadable

   cypress.cy7c429

1.1 

  FIFO:  2K x 9 FIFO
        w/ MR, W, R, XI, and FL/RT; 
        Cascadable

   cypress.pal16l8

1.1 

  PLD:  Industry Standard PLD

   cypress.pal16r4

1.1 

  PLD:  Industry Standard PLD

   cypress.pal16r6

1.1 

  PLD:  Industry Standard PLD

   cypress.pal16r8

1.1 

  PLD:  Industry Standard PLD

   cypress.palc16l8

1.1 

  PLD:  Industry Standard PLD

   cypress.palc16r4

1.1 

  PLD:  Industry Standard PLD

   cypress.pal16r6

1.1 

  PLD:  Industry Standard PLD

   cypress.palc16r8

1.1 

  PLD:  Industry Standard PLD

   cypress.palc22v10d

1.1 

  PLD:  Reprogrammable CMOS 
        PAL (R) Device

   cypress.cypress_utils(body)

1.2 

  Other:  Various support utilities

   cypress.dual_port(body)

1.1 

  Other:  Cypress Dual-Port RAM
        w/ Semaphores, Int, and Busy

   cypress.dual_port_tv(body)

1.1 

  Other:  Timing Package
        for Cypress Dual-Port RAMS

   cypress.pal20_tv(body)

1.1 

  Other:   Industry-Standard PLD, 
        Timing View Package for PAL20 
        Series Devices

   cypress.palc20_tv(body)

1.1 

  Other:  Reprogrammable CMOS PLD,
        Timing View Package for PALC20 
        Series Devices

   cypress.ram_ce(body)

1.1 

  Other:  Cypress RAM 
        w/ one CS and bussed Data Inputs 
        and Data Outputs

   cypress.ram_ce_oe(body)

1.2 

  Other:  Cypress RAM
        w/ one CS, one OE, and shared I/O

   cypress.ram_ce_oe_tv(body)

1.1 

  Other:  Timing Package 
        for RAM devices w/ single CE, 
        single OE, and shared I/O

   cypress.ram_ce_tv(body)

1.1 

  Other:  Timing view package 
        for RAM devices w/ a single CE 
        and shared I/O


   eia

   eia.eia567ev

1.0 

  Other:  EIA-567 Component Modeling 
          Specification:  Electrical View

   eia.eia567pv

1.0 

  Other:  EIA-567 Component Modeling 
          Specification:  Physical View

   eia.eia567tv

1.1 

  Other:  EIA-567 Component Modeling 
          Specification:  Timing View


idt

    idt.idtXXfct841

v1.1 

  Others:  Bus interface latches
           w/ PRE, CLR, LE, and OE.

    idt.idtXXfct646

v1.1 

  Others:  Octal Transceiver/Register
           w/ Enable and Direction Control

    idt.idtXXfct543

v1.1 

  Others:  Octal Latched Transceiver
           w/ Latch Enable, Chip Enable,
           and Output Enable

    idt.pkgs

v1.1 

  Others:  Various packages to be used in
           conjunction with IDT models


   ieee

   ieee.std_logic_1164(body)

1.1 

  Other:  IEEE standard used to describe 
          interconnection data types used 
          in VHDL modeling


   utilities

   utilities.jedec_reader(body)

1.2 

  Other:  Reads jedec file and returns 
        fuse map as a bit_vector.  Fuse 
        checksum also extracted and 
        verified.

   utilities.mem_page_small(body)

1.2 

  Other:  Memory Model Package
        w/ Disk Paging

   utilities.memory(body)

1.2 

  Other:  Support subprograms
        for modeling memory devices

   utilities.standard_utils(body)

1.2 

  Other:  Subprograms for type 
        conversions between types in
        std.standard and other support 
        functions associated with package 
        std.standard

   utilities.std_logic_1164_utils(body)

1.2 

  Other:  Subprograms for type conversions 
        between types in std.standard 
        and ieee.std_logic_1164 and 
        other support functions associated 
        with package ieee.std_logic_1164