-------------------------------------------------------- -- MP3 Soc TOP block -- Date : 2001.5 -- revision 2.0 -- by Jong seok Park --------------------------------------------------------- LIBRARY ieee; USE ieee.std_logic_1164.all; library lpm; USE lpm.LPM_COMPONENTS.all; -- USE work.LPM_COMPONENTS.all; --for simulation ------------------------------------------------------------------------------------ Entity top is Port ( RESET : in std_logic; CLOCK : in std_logic; PROM_OEB, ADDR_ALE, EXT_RAM_WRB, EXT_RAM_RDB, PROM_CSB, EXT_RAM_CSB, EXT_RAM_SEL0B, EXR_RAM_SEL1B : out std_logic; KEYINT0B, KEYINT1B : in std_logic; TXD : out std_logic; RXD : inout std_logic; P0 : inout std_logic_vector(7 downto 0); P1OUT : out std_logic_vector(7 downto 0); P2OUT : out std_logic_vector(7 downto 0); P37_OUT : out std_logic; P36_IN : in std_logic; P35_IN : in std_logic; P34_IN : in std_logic; P33_IN : in std_logic; P32_IN : in std_logic; P31_IN : in std_logic; P30_IN : in std_logic; P40_OUT : out std_logic; -- I2C CLK P41_OUT : out std_logic; -- I2C DATA ----------------- IDE_nRESET : out std_logic; -- CHIP PIN IDE_nDIOW : out std_logic; -- CHIP PIN IDE_nDIOR : out std_logic; -- CHIP PIN IDE_DA2 : out std_logic; -- CHIP PIN IDE_DA1 : out std_logic; -- CHIP PIN IDE_DA0 : out std_logic; -- CHIP PIN IDE_nCS3FX : out std_logic; -- CHIP PIN IDE_nCS1FX : out std_logic; -- CHIP PIN IDE_nDASP : in std_logic; -- CHIP PIN IDE_INTRQ : in std_logic; -- CHIP PIN IDE_IORDY : in std_logic; -- CHIP PIN -- IDE_LSB_DATA : inout std_logic_vector(7 downto 0); IDE_MSB_DATA : inout std_logic_vector(7 downto 0); ----------------- ------------------------------------------------------ SMC_READY_BUSYB : in std_logic; -- CHIP PIN SMC_CEB : out std_logic; -- CHIP PIN SMC_CLE : out std_logic; -- CHIP PIN SMC_ALE : out std_logic; -- CHIP PIN SMC_WEB : out std_logic; -- CHIP PIN SMC_REB : out std_logic; -- CHIP PIN SMC_WPB : out std_logic; BOARDFLASH_READY_BUSYB : in std_logic; -- CHIP PIN BOARDFLASH_CEB : out std_logic; -- CHIP PIN BOARDFLASH_CLE : out std_logic; -- CHIP PIN BOARDFLASH_ALE : out std_logic; -- CHIP PIN BOARDFLASH_WEB : out std_logic; -- CHIP PIN BOARDFLASH_REB : out std_logic; -- CHIP PIN BOARDFLASH_WPB : out std_logic; FLASH_DATA_IO : inout std_logic_vector(7 downto 0); -------------------------------------------------------- CLCD_CS : out std_logic; GLCD_CSB : out std_logic; GLCD_RESET : out std_logic; GLCD_EL_EN : out std_logic; SEGOUT : out std_logic_vector(7 downto 0); T0,T1,T2,T2EX : in std_logic; MP3_REQ : in std_logic; MP3_SDO : out std_logic; MP3_CLK : out std_logic; MMC_CLK : out std_logic; -- CHIP PIN MMC_CMD_SPI_OUT : out std_logic; -- CHIP PIN MMC_DATA_SPI_IN : in std_logic; -- CHIP PIN MMC_VCCEN : out std_logic; -- CHIP PIN MMC_RS_CSB : out std_logic -- CHIP PIN -- for TEST -------------------------------- -- MP3_CNTR_REG : out std_logic_vector(7 downto 0); -- MP3_512_END : out std_logic; -- MP3_CLKEN_REG : out std_logic; -- MP3_CLKEN_REQ : out std_logic; -- MP3DATACOUNT : out std_logic_vector(3 downto 0); -- DMA_RAM_RE_4TEST : out std_logic; -- DMA_RAM_WE_4TEST : out std_logic; -- DMA_RAM_IN_4TEST : out std_logic_vector(7 downto 0); -- DMA_RAM_OUT_4TEST : out std_logic_vector(7 downto 0); -- DMA_RAM_ADDR_4TEST : out std_logic_vector(3 downto 0) ); End top; ------------------------------------------------------------------------------------ Architecture top_a of top is -------------------------------------------------------- -- I80c32/31/52/51 core -- IDEC IP (IP#: IP-PSSFV-000040-01) -- by Jong seok Park, jspark@voiso.com --------------------------------------------------------- component i8032 Port( rst : in std_logic; -- system reset x1 : in std_logic; -- Main clock p0_in : in std_logic_vector(7 downto 0); -- Port 0 INPUT p0_out : out std_logic_vector(7 downto 0); -- Port 0 OUTPUT p0_out_en : out std_logic; -- Port 0 out enable p1_in : in std_logic_vector(7 downto 0); -- Port 1 INPUT p1_out : out std_logic_vector(7 downto 0); -- Port 1 INPUT p2_in : in std_logic_vector(7 downto 0); -- Port 2 INPUT p2_out : out std_logic_vector(7 downto 0); -- Port 2 OUTPUT p3_in : in std_logic_vector(7 downto 0); -- Port 3 INPUT p3_out : out std_logic_vector(7 downto 0); -- Port 3 OUTPUT p4_in : in std_logic_vector(7 downto 0); p4_out : out std_logic_vector(7 downto 0); p5_in : in std_logic_vector(7 downto 0); p5_out : out std_logic_vector(7 downto 0); p6_in : in std_logic_vector(7 downto 0); p6_out : out std_logic_vector(7 downto 0); p7_in : in std_logic_vector(7 downto 0); p7_out : out std_logic_vector(7 downto 0); p8_in : in std_logic_vector(7 downto 0); p8_out : out std_logic_vector(7 downto 0); p9_in : in std_logic_vector(7 downto 0); p9_out : out std_logic_vector(7 downto 0); p4_ext_rd_enb, p5_ext_rd_enb, p6_ext_rd_enb, p7_ext_rd_enb, p8_ext_rd_enb, p9_ext_rd_enb : in std_logic; int_data_bus : inout std_logic_vector(7 downto 0); psenb : out std_logic; ale : out std_logic; int0b_pin,int1b_pin,t0_pin,t1_pin : in std_logic; ext_wrb_pin,ext_rdb_pin,txd_pin : out std_logic; t2,t2ex : in std_logic; -- only 80c32 rxd_in : in std_logic; rxd_out,send : out std_logic; int_ram_addr : out std_logic_vector(7 downto 0); int_ram_oeb : out std_logic; int_ram_web : out std_logic; x2 : out std_logic; -- x1/2 Mhz ------------ for MP3 -------------------------- MP3_REQ : in std_logic; MP3_SDO : out std_logic; MP3_CLK : out std_logic; FLASH_DATA_IO : inout std_logic_vector(7 downto 0); SMC_READY_BUSYB : in std_logic; -- CHIP PIN SMC_CEB : out std_logic; -- CHIP PIN SMC_CLE : out std_logic; -- CHIP PIN SMC_ALE : out std_logic; -- CHIP PIN SMC_WEB : out std_logic; -- CHIP PIN SMC_REB : out std_logic; -- CHIP PIN BOARDFLASH_READY_BUSYB : in std_logic; -- CHIP PIN BOARDFLASH_CEB : out std_logic; -- CHIP PIN BOARDFLASH_CLE : out std_logic; -- CHIP PIN BOARDFLASH_ALE : out std_logic; -- CHIP PIN BOARDFLASH_WEB : out std_logic; -- CHIP PIN BOARDFLASH_REB : out std_logic; -- CHIP PIN MMC_CLK : out std_logic; -- CHIP PIN MMC_CMD_SPI_OUT : out std_logic; -- CHIP PIN MMC_DATA_SPI_IN : in std_logic; -- CHIP PIN MMC_VCCEN : out std_logic; -- CHIP PIN MMC_RS_CSB : out std_logic; -- CHIP PIN ----------------- IDE_nRESET : out std_logic; -- CHIP PIN IDE_nDIOW : out std_logic; -- CHIP PIN IDE_nDIOR : out std_logic; -- CHIP PIN IDE_DA2 : out std_logic; -- CHIP PIN IDE_DA1 : out std_logic; -- CHIP PIN IDE_DA0 : out std_logic; -- CHIP PIN IDE_nCS3FX : out std_logic; -- CHIP PIN IDE_nCS1FX : out std_logic; -- CHIP PIN IDE_nDASP : in std_logic; -- CHIP PIN IDE_INTRQ : in std_logic; -- CHIP PIN IDE_IORDY : in std_logic; -- CHIP PIN IDE_LSB_DATA : inout std_logic_vector(7 downto 0); IDE_MSB_DATA : inout std_logic_vector(7 downto 0) ----------------- -- for TEST -------------------------------- -- MP3_CNTR_REG : out std_logic_vector(7 downto 0); -- MP3_512_END : out std_logic; -- MP3_CLKEN_REG : out std_logic; -- MP3_CLKEN_REQ : out std_logic; -- MP3DATACOUNT : out std_logic_vector(3 downto 0); -- DMA_RAM_RE_4TEST : out std_logic; -- DMA_RAM_WE_4TEST : out std_logic; -- DMA_RAM_IN_4TEST : out std_logic_vector(7 downto 0); -- DMA_RAM_OUT_4TEST : out std_logic_vector(7 downto 0); -- DMA_RAM_ADDR_4TEST : out std_logic_vector(3 downto 0) ); End component; --component opndrn8bit -- Port ( -- opndrn8_in : in std_logic_vector(7 downto 0); -- opndrn8_out : out std_logic_vector(7 downto 0) -- ); --End component; -- for i8032 port signal --------- signal rst,x1 : std_logic; signal x2 : std_logic; signal p0_in : std_logic_vector(7 downto 0); -- Port 0 INPUT signal p0_out : std_logic_vector(7 downto 0); -- Port 0 OUTPUT signal p0_out_en : std_logic; -- Port 0 out enable signal p1_in : std_logic_vector(7 downto 0); signal p1_out : std_logic_vector(7 downto 0); signal p2_in : std_logic_vector(7 downto 0); -- Port 2 INPUT signal p2_out : std_logic_vector(7 downto 0); -- Port 2 OUTPUT signal p3_in : std_logic_vector(7 downto 0); -- Port 3 INPUT signal p3_out : std_logic_vector(7 downto 0); -- Port 3 OUTPUT signal p4_in : std_logic_vector(7 downto 0); signal p4_out : std_logic_vector(7 downto 0); signal p5_in : std_logic_vector(7 downto 0); signal p5_out : std_logic_vector(7 downto 0); signal p6_in : std_logic_vector(7 downto 0); signal p6_out : std_logic_vector(7 downto 0); signal p7_in : std_logic_vector(7 downto 0); signal p7_out : std_logic_vector(7 downto 0); signal p8_in : std_logic_vector(7 downto 0); signal p8_out : std_logic_vector(7 downto 0); signal p9_in : std_logic_vector(7 downto 0); signal p9_out : std_logic_vector(7 downto 0); signal int_data_bus : std_logic_vector(7 downto 0); signal psenb : std_logic; signal ale : std_logic; signal int0b_pin,int1b_pin,t0_pin,t1_pin : std_logic; signal ext_wrb_pin,ext_rdb_pin,txd_pin : std_logic; signal t2_pin,t2ex_pin : std_logic; -- only 80c32 signal rxd_in : std_logic; signal rxd_out,send : std_logic; signal int_ram_addr : std_logic_vector(7 downto 0); signal int_ram_oeb : std_logic; signal int_ram_web : std_logic; --signal mac_cycle_out : std_logic_vector(2 downto 0); --signal mac_state_out : std_logic_vector(3 downto 0); --signal check_ir_out : std_logic_vector(7 downto 0); -- for modeing INT_RAM for LPM_RAM_DQ --------- signal int_ram_out : std_logic_vector(7 downto 0); signal int_ram_we : std_logic; signal VCC_H : std_logic; -- for ext_Address latch signal ext_address_low, ext_address_high : std_logic_vector(7 downto 0); -- for 7 segment display signal segment_buffer : std_logic_vector(3 downto 0); signal FLASH_DATABUS_ENB : std_logic; signal p4_ext_rd_enb : std_logic; signal p5_ext_rd_enb : std_logic; signal p6_ext_rd_enb : std_logic; signal p7_ext_rd_enb : std_logic; signal p8_ext_rd_enb : std_logic; signal p9_ext_rd_enb : std_logic; Begin VCC_H <= '1'; -------------------------------------------------------- -- I80c32/31/52/51 core -- IDEC IP (IP#: IP-PSSFV-000040-01) -- by Jong seok Park, jspark@voiso.com --------------------------------------------------------- u1: i8032 port map ( rst, x1 , p0_in, p0_out, p0_out_en, p1_in, p1_out, p2_in , p2_out, p3_in , p3_out, p4_in, p4_out, p5_in, p5_out, p6_in, p6_out, p7_in, p7_out, p8_in, p8_out, p9_in, p9_out, p4_ext_rd_enb, p5_ext_rd_enb, p6_ext_rd_enb, p7_ext_rd_enb, p8_ext_rd_enb, p9_ext_rd_enb, int_data_bus, psenb , ale , int0b_pin,int1b_pin,t0_pin,t1_pin, ext_wrb_pin,ext_rdb_pin,txd_pin, t2_pin,t2ex_pin, rxd_in, rxd_out,send, int_ram_addr, int_ram_oeb, int_ram_web, x2, MP3_REQ, MP3_SDO, MP3_CLK, FLASH_DATA_IO, SMC_READY_BUSYB , SMC_CEB , SMC_CLE , SMC_ALE , SMC_WEB , SMC_REB , BOARDFLASH_READY_BUSYB , BOARDFLASH_CEB , BOARDFLASH_CLE , BOARDFLASH_ALE , BOARDFLASH_WEB , BOARDFLASH_REB , MMC_CLK , MMC_CMD_SPI_OUT , MMC_DATA_SPI_IN , MMC_VCCEN, MMC_RS_CSB, ----------------- IDE_nRESET, IDE_nDIOW, IDE_nDIOR, IDE_DA2, IDE_DA1, IDE_DA0, IDE_nCS3FX, IDE_nCS1FX, IDE_nDASP, IDE_INTRQ, IDE_IORDY, ---- IDE_LSB_DATA, -- same pin place FLASH_DATA_IO, IDE_MSB_DATA ----------------- -- for TEST -------------------------------- -- MP3_CNTR_REG , -- MP3_512_END, -- MP3_CLKEN_REG, -- MP3_CLKEN_REQ, -- MP3DATACOUNT, -- DMA_RAM_RE_4TEST , -- DMA_RAM_WE_4TEST , -- DMA_RAM_IN_4TEST , -- DMA_RAM_OUT_4TEST , -- DMA_RAM_ADDR_4TEST ); ------------------------------------------------- -- MODELING INT_RAM with LPM_RAM_DQ ------------------------------------------------- u2: lpm_ram_dq GENERIC MAP( LPM_WIDTH => 8, LPM_WIDTHAD => 8, LPM_INDATA => "UNREGISTERED", LPM_ADDRESS_CONTROL => "UNREGISTERED", LPM_OUTDATA => "REGISTERED" ) PORT MAP( data => int_data_bus, address => int_ram_addr, we => int_ram_we, q => int_ram_out, -- before TRI --inclock => VCC_H, inclock => x2, -- jspark 2001_08_31 outclock => x2 ); int_ram_we <= not int_ram_web; process(int_ram_out,int_ram_oeb, int_ram_web) begin if ( int_ram_web and not int_ram_oeb)='1' then int_data_bus <= int_ram_out; else int_data_bus <= "ZZZZZZZZ"; end if; end process; ------------------------------------------------- rst <= RESET; x1 <= CLOCK; PROM_OEB <= psenb; ADDR_ALE <= ale; PROM_CSB <='0'; EXT_RAM_CSB <= '0'; EXT_RAM_SEL0B <='0'; EXR_RAM_SEL1B <='1'; ---------------------------------------- -- P0 inout modeling ---------------------------------------- process(p0_out, p0_out_en,P0) begin if p0_out_en='1' then P0 <= p0_out; else P0 <= "ZZZZZZZZ"; -- P0 output end if; p0_in <= P0; -- P0 input end process; --------------------------------------- P1OUT <= p1_out; p1_in <= "00000000"; P2OUT <= p2_out; p2_in <= "00000000"; -- P3OUT <= p3_out; -- p3_in <= "00000011"; -- FOR KEY CONTROL P37_OUT <= p3_out(7); p3_in(7) <= '0'; p3_in(6) <= P36_IN; p3_in(5) <= P35_IN; p3_in(4) <= P34_IN; p3_in(3) <= P33_IN; p3_in(2) <= P32_IN; p3_in(1) <= P31_IN; p3_in(0) <= P30_IN; ---------------------------- -- for I2C port P40_OUT <= p4_out(0); -- I2C CLK P41_OUT <= p4_out(1); -- I2C DATA int0b_pin <= KEYINT0B; int1b_pin <= KEYINT1B; t0_pin <= T0; t1_pin <= T1; t2_pin <= T2; t2ex_pin <= T2EX; EXT_RAM_WRB <=ext_wrb_pin; EXT_RAM_RDB <=ext_rdb_pin; TXD <=txd_pin; process(send,rxd_out,RXD) begin if send='1' then RXD <= rxd_out; else RXD <= 'Z'; end if; rxd_in <= RXD; end process; --------------- --------------------------------------------- -- ext address low latch ==> modified by jspark 2001_08_31, D_FF --------------------------------------------- --process(p0_out,ale,reset,ext_address_low) process(p0_out,ale,reset,ext_address_low,x2) begin if reset='1' then ext_address_low <= "00000000"; elsif x2='0' and x2'event then -- added by jspark 2001_08_31 if ale='1' then ext_address_low <= p0_out; else ext_address_low <= ext_address_low; end if; end if; end process; ext_address_high <= p2_out; -------------------------------------------- -------------------------------------------------------------------------------------- -- character LCD CS -------------------------------------------------------------------------------------- -- 0xFFFC - 0xFFFF -- 0xFFFC -- 0xFFFD -- 0xFFFE -- 0xFFFF process(ext_address_high,ext_address_low,ext_wrb_pin,ext_rdb_pin,reset) begin if reset='1' then CLCD_CS <= '0'; elsif ((ext_address_high="11111111" and ext_address_low(7 downto 2)="111111") and (ext_rdb_pin='0' or ext_wrb_pin='0')) then CLCD_CS <= '1'; else CLCD_CS <= '0'; end if; end process; -------------------------------------------------------------------------------------- -- graphic LCD CS -------------------------------------------------------------------------------------- -- 0xFFF0 - 0xFFF7 -- 0xFFF5 DATA write * -- 0xFFF6 DATA read -- 0xFFF1 CMD write * -- 0xFFF2 CMD read process(ext_address_high,ext_address_low,ext_wrb_pin,ext_rdb_pin,reset) begin if reset='1' then GLCD_CSB <= '1'; elsif ((ext_address_high="11111111" and ext_address_low(7 downto 3)="11110") and (ext_rdb_pin='0' or ext_wrb_pin='0')) then GLCD_CSB <= '0'; else GLCD_CSB <= '1'; end if; end process; GLCD_RESET <= p9_out(7); GLCD_EL_EN <= p9_out(6); -------------------------------------------------------------------------------------- -- 7 SEG DISPLAY -------------------------------------------------------------------------------------- -- 0xFFFB process(x2,ext_address_high,ext_address_low,ext_wrb_pin,reset,segment_buffer,p0_out) begin if reset='1' then segment_buffer <= "0000"; -- elsif ((ext_address_high="11111111" and ext_address_low="11111011") and -- (ext_wrb_pin='0')) then elsif x2='0' and x2'event then if ext_wrb_pin='0' then if (ext_address_high="11111111" and ext_address_low="11111011") then segment_buffer <= p0_out(3 downto 0); else segment_buffer <= segment_buffer; end if; else segment_buffer <= segment_buffer; end if; end if; end process; process(segment_buffer) begin case segment_buffer is when "0000" => SEGOUT <= "00000010"; -- 0 when "0001" => SEGOUT <= "10011111"; -- 1 when "0010" => SEGOUT <= "00100101"; -- 2 when "0011" => SEGOUT <= "00001101"; -- 3 when "0100" => SEGOUT <= "10011001"; -- 4 when "0101" => SEGOUT <= "01001001"; -- 5 when "0110" => SEGOUT <= "01000001"; -- 6 when "0111" => SEGOUT <= "00011111"; -- 7 when "1000" => SEGOUT <= "00000001"; -- 8 when "1001" => SEGOUT <= "00001001"; -- 9 when others => SEGOUT <= "00000000"; -- full display end case; end process; ----------------------------------- -- P4 : IDE CONTROL INPUT ----------------------------------- --p4_in(7) <= IDE_IORDY; --p4_in(6) <= IDE_INTREQ; --p4_in(5) <= IDE_nDASP; --p4_in(4 downto 0) <= "00000"; ----------------------------------- -- P5 : IDE CONTROL OUPUT ----------------------------------- --IDE_nDIOW <= p5_out(7); --IDE_nDIOR <= p5_out(6); --IDE_nCS3FX <= p5_out(5); --IDE_nCS1FX <= p5_out(4); --IDE_DA2 <= p5_out(3); --IDE_DA1 <= p5_out(2); --IDE_DA0 <= p5_out(1); ----------------------------------- -- P7 : HDD_MSB DATA ----------------------------------- --IDE_MSB_DATA <= p7_out when p5_out(7)='0' else -- "ZZZZZZZZ"; --p7_in <= IDE_MSB_DATA; ------------------------------------------------ -- P6 : HDD_LSB DATA / P9 : FLASH DATA BUS ------------------------------------------------- --IDE_LSB_DATA <= p6_out when (FLASH_DATABUS_ENB='1' and p5_out(7)='0') else -- IDE -- p9_out when (FLASH_DATABUS_ENB='0' and p8_out(3)='0') else -- FLASH -- "ZZZZZZZZ"; --p6_in <= IDE_LSB_DATA; --p9_in <= IDE_LSB_DATA; --p4_ext_rd_enb <= '0'; -- for NOT DATABUS as IDE control INPUT --p5_ext_rd_enb <= '0'; -- for NOT DATABUS as IDE control OUTPUT --p6_ext_rd_enb <= p5_out(6); -- for IDE LOW DATABUS --p7_ext_rd_enb <= p5_out(6); -- for IDE HIGH DATABUS --p8_ext_rd_enb <= '0'; -- for NOT DATABUS , as FLASH CONTROL OUTPUT --p9_ext_rd_enb <= p8_out(2); -- for FLASH DATABUS ext read enable SMC_WPB <= '1'; BOARDFLASH_WPB <= '1'; End top_a; ---------------------------------------------------------