-------------------------------------------------------- -- IDE interface for MP3 Soc -- Date : 2001.5 -- revision 2.0 -- by Jong seok Park --------------------------------------------------------- library IEEE; use IEEE.std_logic_1164.all; use ieee.std_logic_arith.all; use ieee.std_logic_unsigned.all; Entity ide_con_blk is port ( reset, clock : in std_logic; -- for using X1/2 160ns int_data_bus : inout std_logic_vector(7 downto 0); ide_con0_reg_we, ide_con0_reg_re, ide_con1_reg_we, ide_con1_reg_re, ide_lsb_reg_we, ide_lsb_reg_re, ide_msb_reg_we, ide_msb_reg_re : in std_logic; IDE_nRESET : out std_logic; -- CHIP PIN IDE_nDIOW : out std_logic; -- CHIP PIN IDE_nDIOR : out std_logic; -- CHIP PIN IDE_DA2 : out std_logic; -- CHIP PIN IDE_DA1 : out std_logic; -- CHIP PIN IDE_DA0 : out std_logic; -- CHIP PIN IDE_nCS3FX : out std_logic; -- CHIP PIN IDE_nCS1FX : out std_logic; -- CHIP PIN IDE_nDASP : in std_logic; -- CHIP PIN IDE_INTRQ : in std_logic; -- CHIP PIN IDE_IORDY : in std_logic; -- CHIP PIN IDE_LSB_DATA : inout std_logic_vector(7 downto 0); IDE_MSB_DATA : inout std_logic_vector(7 downto 0) -- DMA_ADDRESS : out std_logic_vector(9 downto 0); -- DMA_WE : out std_logic -- DMA_RE : out std_logic ); End ide_con_blk; ---------------------------------------------------------- Architecture ide_con_blk_a of ide_con_blk is component ide_con0_reg port ( reset,clock : in std_logic; re,we : in std_logic; int_data_bus : inout std_logic_vector(7 downto 0); IDE_nRESET : out std_logic; -- CHIP PIN IDE_nDIOW : out std_logic; -- CHIP PIN IDE_nDIOR : out std_logic; -- CHIP PIN IDE_DA2 : out std_logic; -- CHIP PIN IDE_DA1 : out std_logic; -- CHIP PIN IDE_DA0 : out std_logic; -- CHIP PIN IDE_nCS3FX : out std_logic; -- CHIP PIN IDE_nCS1FX : out std_logic -- CHIP PIN ); end component; component ide_con1_reg port ( reset,clock : in std_logic; re,we : in std_logic; int_data_bus : inout std_logic_vector(7 downto 0); IDE_nDASP : in std_logic; -- CHIP PIN IDE_INTRQ : in std_logic; -- CHIP PIN IDE_IORDY : in std_logic -- CHIP PIN ); end component; component ide_lsb_reg port ( reset,clock : in std_logic; re,we : in std_logic; int_data_bus : inout std_logic_vector(7 downto 0); IDE_nDIOW : in std_logic; IDE_nDIOR : in std_logic; IDE_LSB_DATA : inout std_logic_vector(7 downto 0) ); end component; component ide_msb_reg port ( reset,clock : in std_logic; re,we : in std_logic; int_data_bus : inout std_logic_vector(7 downto 0); IDE_nDIOW : in std_logic; IDE_nDIOR : in std_logic; IDE_MSB_DATA : inout std_logic_vector(7 downto 0) ); end component; signal IDE_nDIOW_sig : std_logic; signal IDE_nDIOR_sig : std_logic; Begin u1 : ide_con0_reg port map ( reset => reset, clock => clock, re => ide_con0_reg_re, we => ide_con0_reg_we, int_data_bus => int_data_bus, IDE_nRESET => IDE_nRESET, IDE_nDIOW => IDE_nDIOW_sig, IDE_nDIOR => IDE_nDIOR_sig, IDE_DA2 => IDE_DA2, IDE_DA1 => IDE_DA1, IDE_DA0 => IDE_DA0, IDE_nCS3FX => IDE_nCS3FX, IDE_nCS1FX => IDE_nCS1FX ); u2 : ide_con1_reg port map ( reset => reset, clock => clock, re => ide_con1_reg_re, we => ide_con1_reg_we, int_data_bus => int_data_bus, IDE_nDASP => IDE_nDASP, IDE_INTRQ => IDE_INTRQ, IDE_IORDY => IDE_IORDY ); u3 : ide_lsb_reg port map ( reset => reset, clock => clock, re => ide_lsb_reg_re, we => ide_lsb_reg_we, int_data_bus => int_data_bus, IDE_nDIOW => IDE_nDIOW_sig, IDE_nDIOR => IDE_nDIOR_sig, IDE_LSB_DATA => IDE_LSB_DATA ); u4 : ide_msb_reg port map ( reset => reset, clock => clock, re => ide_msb_reg_re, we => ide_msb_reg_we, int_data_bus => int_data_bus, IDE_nDIOW => IDE_nDIOW_sig, IDE_nDIOR => IDE_nDIOR_sig, IDE_MSB_DATA => IDE_MSB_DATA ); IDE_nDIOW <= IDE_nDIOW_sig; IDE_nDIOR <= IDE_nDIOR_sig; end ide_con_blk_a; ---------------------------------------------------------------------- library IEEE; use IEEE.std_logic_1164.all; ---------------------------------------------------------------------- Entity ide_con0_reg is port ( reset,clock : in std_logic; re,we : in std_logic; int_data_bus : inout std_logic_vector(7 downto 0); IDE_nRESET : out std_logic; -- CHIP PIN IDE_nDIOW : out std_logic; -- CHIP PIN IDE_nDIOR : out std_logic; -- CHIP PIN IDE_DA2 : out std_logic; -- CHIP PIN IDE_DA1 : out std_logic; -- CHIP PIN IDE_DA0 : out std_logic; -- CHIP PIN IDE_nCS3FX : out std_logic; -- CHIP PIN IDE_nCS1FX : out std_logic -- CHIP PIN ); end ide_con0_reg; ---------------------------------------------------------------------- Architecture ide_con0_reg_a of ide_con0_reg is signal ide_con0_reg_sig : std_logic_vector(7 downto 0); begin Process(reset,clock,we,int_data_bus,ide_con0_reg_sig) begin if reset='1' then ide_con0_reg_sig <= "00000000"; elsif clock='0' and clock'event then if we='1' then ide_con0_reg_sig <= int_data_bus; else ide_con0_reg_sig <= ide_con0_reg_sig; end if; end if; end process; IDE_nRESET <= ide_con0_reg_sig(7); IDE_nDIOW <= ide_con0_reg_sig(6); IDE_nDIOR <= ide_con0_reg_sig(5); IDE_DA2 <= ide_con0_reg_sig(4); IDE_DA1 <= ide_con0_reg_sig(3); IDE_DA0 <= ide_con0_reg_sig(2); IDE_nCS3FX <= ide_con0_reg_sig(1); IDE_nCS1FX <= ide_con0_reg_sig(0); int_data_bus <= ide_con0_reg_sig when re='1' else "ZZZZZZZZ"; end ide_con0_reg_a; ---------------------------------------------------------------------- library IEEE; use IEEE.std_logic_1164.all; ---------------------------------------------------------------------- Entity ide_con1_reg is port ( reset,clock : in std_logic; re,we : in std_logic; int_data_bus : inout std_logic_vector(7 downto 0); IDE_nDASP : in std_logic; -- CHIP PIN IDE_INTRQ : in std_logic; -- CHIP PIN IDE_IORDY : in std_logic -- CHIP PIN ); end ide_con1_reg; architecture ide_con1_reg_a of ide_con1_reg is signal ide_con1_reg_sig : std_logic_vector(7 downto 0); begin Process(reset,clock,we,int_data_bus,IDE_nDASP) begin if reset='1' then ide_con1_reg_sig(7) <= '0'; elsif clock='0' and clock'event then ide_con1_reg_sig(7) <= IDE_nDASP; end if; end process; Process(reset,clock,we,int_data_bus,IDE_INTRQ) begin if reset='1' then ide_con1_reg_sig(6) <= '0'; elsif clock='0' and clock'event then ide_con1_reg_sig(6) <= IDE_INTRQ; end if; end process; Process(reset,clock,we,int_data_bus,IDE_IORDY) begin if reset='1' then ide_con1_reg_sig(5) <= '0'; elsif clock='0' and clock'event then ide_con1_reg_sig(5) <= IDE_IORDY; end if; end process; Process(reset,clock,we,int_data_bus,ide_con1_reg_sig) begin if reset='1' then ide_con1_reg_sig(4 downto 0) <= "00000"; elsif clock='0' and clock'event then if we='1' then ide_con1_reg_sig(4 downto 0) <= int_data_bus(4 downto 0); else ide_con1_reg_sig(4 downto 0) <= ide_con1_reg_sig(4 downto 0); end if; end if; end process; int_data_bus <= ide_con1_reg_sig when re='1' else "ZZZZZZZZ"; End ide_con1_reg_a; ---------------------------------------------------------------------- library IEEE; use IEEE.std_logic_1164.all; ---------------------------------------------------------------------- Entity ide_lsb_reg is port ( reset,clock : in std_logic; re,we : in std_logic; int_data_bus : inout std_logic_vector(7 downto 0); IDE_nDIOW : in std_logic; IDE_nDIOR : in std_logic; IDE_LSB_DATA : inout std_logic_vector(7 downto 0) ); end ide_lsb_reg; architecture ide_lsb_reg_a of ide_lsb_reg is signal ide_lsb_sig : std_logic_vector(7 downto 0); begin Process(reset,clock,we,int_data_bus,ide_lsb_sig, IDE_nDIOR) begin if reset='1' then ide_lsb_sig <= "00000000"; elsif clock='0' and clock'event then if we='1' then ide_lsb_sig <= int_data_bus; elsif IDE_nDIOR='0' then ide_lsb_sig <= IDE_LSB_DATA; else ide_lsb_sig <= ide_lsb_sig; end if; end if; end process; int_data_bus <= ide_lsb_sig when re='1' else "ZZZZZZZZ"; IDE_LSB_DATA <= ide_lsb_sig when IDE_nDIOW='0' else "ZZZZZZZZ"; End ide_lsb_reg_a; ------------------------------------------------------------------- library IEEE; use IEEE.std_logic_1164.all; ---------------------------------------------------------------------- Entity ide_msb_reg is port ( reset,clock : in std_logic; re,we : in std_logic; int_data_bus : inout std_logic_vector(7 downto 0); IDE_nDIOW : in std_logic; IDE_nDIOR : in std_logic; IDE_MSB_DATA : inout std_logic_vector(7 downto 0) ); end ide_msb_reg; architecture ide_msb_reg_a of ide_msb_reg is signal ide_msb_sig : std_logic_vector(7 downto 0); begin Process(reset,clock,we,int_data_bus,ide_msb_sig, IDE_nDIOR) begin if reset='1' then ide_msb_sig <= "00000000"; elsif clock='0' and clock'event then if we='1' then ide_msb_sig <= int_data_bus; elsif IDE_nDIOR='0' then ide_msb_sig <= IDE_MSB_DATA; else ide_msb_sig <= ide_msb_sig; end if; end if; end process; int_data_bus <= ide_msb_sig when re='1' else "ZZZZZZZZ"; IDE_MSB_DATA <= ide_msb_sig when IDE_nDIOW='0' else "ZZZZZZZZ"; End ide_msb_reg_a; -------------------------------------------------------------------