-------------------------------------------------------- -- DMA interface for MP3 SoC with 80c51 core -- Date : 2001.5 -- revision 2.0 -- by Jong seok Park --------------------------------------------------------- library IEEE; use IEEE.std_logic_1164.all; use ieee.std_logic_arith.all; use ieee.std_logic_unsigned.all; Entity DMA_BLK is port ( reset, clock : in std_logic; -- for using X1/2 160ns int_data_bus : inout std_logic_vector(7 downto 0); dma_con_reg_we, dma_con_reg_re, -- DMA_CON register dma_addr_high_reg_we, dma_addr_high_reg_re, -- DMA_ADDR_HIGH dma_addr_low_reg_we, -- DMA_ADDR_LOW dma_addr_low_reg_re, dma_data_reg_we, -- DMA_DATA (actually RAM Array) dma_data_reg_re : in std_logic; flash_data_in : in std_logic_vector(7 downto 0); flash_data_out : out std_logic_vector(7 downto 0); flash_dma_addr : in std_logic_vector(9 downto 0); flash_dma_we : in std_logic; flash_dma_re : in std_logic; -- MMC mmc2dma_data : in std_logic_vector(7 downto 0); mmc_dma_addr : in std_logic_vector(9 downto 0); mmc_dma_we : in std_logic; -- MMC mp3_dma_data_out : out std_logic_vector(7 downto 0); mp3_dma_addr : in std_logic_vector(9 downto 0); mp3_dma_re : in std_logic -- for TEST -------------------------------- -- DMA_RAM_RE_4TEST : out std_logic; -- DMA_RAM_WE_4TEST : out std_logic; -- DMA_RAM_IN_4TEST : out std_logic_vector(7 downto 0); -- DMA_RAM_OUT_4TEST : out std_logic_vector(7 downto 0); -- DMA_RAM_ADDR_4TEST : out std_logic_vector(3 downto 0) ); End DMA_BLK; ---------------------------------------------------------- Architecture DMA_BLK_A of DMA_BLK is component DMA_CON_REG port ( clock,reset : in std_logic; int_data_bus : inout std_logic_vector(7 downto 0); dma_con_reg_we, dma_con_reg_re : in std_logic; c51_dma_access : out std_logic; flash_dma_access : out std_logic; mp3_dma_access : out std_logic; -- MMC mmc_dma_access : out std_logic; -- MMC dma_data_reg_write_flagb : out std_logic ); end component; component DMA_ADDR_REG -- for C51 access port ( clock,reset : in std_logic; int_data_bus : inout std_logic_vector(7 downto 0); dma_addr_high_reg_we, dma_addr_high_reg_re, dma_addr_low_reg_we, dma_addr_low_reg_re : in std_logic; c51_dma_addr : out std_logic_vector(10 downto 0) ); end component; component DMA_RAM_ARRAY port ( clock,reset : in std_logic; int_data_bus : inout std_logic_vector(7 downto 0); c51_dma_access, flash_dma_access, mp3_dma_access : in std_logic; -- for indication DMA user -- MMC mmc_dma_access : in std_logic; -- for indication DMA user -- MMC dma_data_reg_write_flagb : in std_logic; dma_data_reg_we, dma_data_reg_re : in std_logic; -- for C51 SFR access flash_dma_we, flash_dma_re : in std_logic; -- for FLASH controller access -- MMC mmc_dma_we : in std_logic; -- MMC c51_dma_addr : in std_logic_vector(10 downto 0); -- for C51 flash_dma_addr : in std_logic_vector(9 downto 0); --for FLASH controller -- MMC mmc2dma_data : in std_logic_vector(7 downto 0); mmc_dma_addr : in std_logic_vector(9 downto 0); -- MMC flash_data_in : in std_logic_vector(7 downto 0); flash_data_out : out std_logic_vector(7 downto 0); mp3_dma_re : in std_logic; mp3_dma_addr : in std_logic_vector(9 downto 0); mp3_dma_data_out : out std_logic_vector(7 downto 0) -- for TEST -------------------------------- -- DMA_RAM_RE_4TEST : out std_logic; -- DMA_RAM_WE_4TEST : out std_logic; -- DMA_RAM_IN_4TEST : out std_logic_vector(7 downto 0); -- DMA_RAM_OUT_4TEST : out std_logic_vector(7 downto 0); -- DMA_RAM_ADDR_4TEST : out std_logic_vector(3 downto 0) ); end component; signal c51_dma_access : std_logic; signal flash_dma_access : std_logic; signal mp3_dma_access : std_logic; -- MMC signal mmc_dma_access : std_logic; -- MMC signal c51_dma_addr : std_logic_vector(10 downto 0); ---for test signal int_data_bus0 : std_logic_vector(7 downto 0); signal dma_data_reg_write_flagb : std_logic; begin u1: DMA_CON_REG port map ( clock => clock, reset => reset, int_data_bus => int_data_bus, dma_con_reg_we => dma_con_reg_we, dma_con_reg_re => dma_con_reg_re, c51_dma_access => c51_dma_access, flash_dma_access => flash_dma_access, mp3_dma_access => mp3_dma_access, -- MMC mmc_dma_access => mmc_dma_access, -- MMC dma_data_reg_write_flagb => dma_data_reg_write_flagb ); u2 : DMA_ADDR_REG port map ( clock => clock, reset => reset, int_data_bus => int_data_bus, dma_addr_high_reg_we => dma_addr_high_reg_we, dma_addr_high_reg_re => dma_addr_high_reg_re, dma_addr_low_reg_we => dma_addr_low_reg_we, dma_addr_low_reg_re => dma_addr_low_reg_re, c51_dma_addr => c51_dma_addr ); u3: DMA_RAM_ARRAY port map ( clock => clock, reset => reset, int_data_bus => int_data_bus, c51_dma_access => c51_dma_access, flash_dma_access => flash_dma_access, mp3_dma_access => mp3_dma_access, -- MMC mmc_dma_access => mmc_dma_access, -- MMC dma_data_reg_write_flagb => dma_data_reg_write_flagb, dma_data_reg_we => dma_data_reg_we, dma_data_reg_re => dma_data_reg_re, flash_dma_we => flash_dma_we, flash_dma_re => flash_dma_re, -- MMC mmc_dma_we => mmc_dma_we, -- MMC c51_dma_addr => c51_dma_addr, flash_dma_addr => flash_dma_addr, -- MMC mmc2dma_data => mmc2dma_data, mmc_dma_addr => mmc_dma_addr, -- MMC flash_data_in => flash_data_in, flash_data_out => flash_data_out, mp3_dma_re => mp3_dma_re, mp3_dma_addr => mp3_dma_addr, mp3_dma_data_out => mp3_dma_data_out -- for TEST -------------------------------- -- DMA_RAM_RE_4TEST => DMA_RAM_RE_4TEST, -- DMA_RAM_WE_4TEST => DMA_RAM_WE_4TEST, -- DMA_RAM_IN_4TEST => DMA_RAM_IN_4TEST, -- DMA_RAM_OUT_4TEST => DMA_RAM_OUT_4TEST, -- DMA_RAM_ADDR_4TEST => DMA_RAM_ADDR_4TEST ); End DMA_BLK_A; --******************************************************************************** library IEEE; use IEEE.std_logic_1164.all; ---------------------------------------------------------------------- Entity DMA_CON_REG is port ( clock,reset : in std_logic; int_data_bus : inout std_logic_vector(7 downto 0); dma_con_reg_we, dma_con_reg_re : in std_logic; c51_dma_access : out std_logic; flash_dma_access : out std_logic; mp3_dma_access : out std_logic; -- MMC mmc_dma_access : out std_logic; -- MMC dma_data_reg_write_flagb : out std_logic ); end DMA_CON_REG; ---------------------------------------------------------------------- Architecture DMA_CON_REG_A of DMA_CON_REG is signal DMA_CON_REG_sig : std_logic_vector(7 downto 0); begin Process(reset,clock,dma_con_reg_we,int_data_bus,DMA_CON_REG_sig) begin if reset='1' then DMA_CON_REG_sig <= "00000000"; elsif clock='0' and clock'event then if dma_con_reg_we='1' then DMA_CON_REG_sig <= int_data_bus; else DMA_CON_REG_sig <= DMA_CON_REG_sig; end if; end if; end process; c51_dma_access <= DMA_CON_REG_sig(7); flash_dma_access <= DMA_CON_REG_sig(6); mp3_dma_access <= DMA_CON_REG_sig(5); -- MMC mmc_dma_access <= DMA_CON_REG_sig(4); -- MMC dma_data_reg_write_flagb <= DMA_CON_REG_sig(0); int_data_bus <= DMA_CON_REG_sig when dma_con_reg_re='1' else "ZZZZZZZZ"; End DMA_CON_REG_A; --******************************************************************************** library IEEE; use IEEE.std_logic_1164.all; ---------------------------------------------------------------------- Entity DMA_ADDR_REG is port ( clock,reset : in std_logic; int_data_bus : inout std_logic_vector(7 downto 0); dma_addr_high_reg_we, dma_addr_high_reg_re, dma_addr_low_reg_we, dma_addr_low_reg_re : in std_logic; c51_dma_addr : out std_logic_vector(10 downto 0) ); end DMA_ADDR_REG; architecture DMA_ADDR_REG_a of DMA_ADDR_REG is signal DMA_ADDR_HIGH_REG_sig : std_logic_vector(7 downto 0); signal DMA_ADDR_LOW_REG_sig : std_logic_vector(7 downto 0); begin Process(reset,clock,dma_addr_high_reg_we,int_data_bus,DMA_ADDR_HIGH_REG_sig) begin if reset='1' then DMA_ADDR_HIGH_REG_sig <= "00000000"; elsif clock='0' and clock'event then if dma_addr_high_reg_we='1' then DMA_ADDR_HIGH_REG_sig <= int_data_bus; else DMA_ADDR_HIGH_REG_sig <= DMA_ADDR_HIGH_REG_sig; end if; end if; end process; Process(reset,clock,dma_addr_low_reg_we,int_data_bus,DMA_ADDR_LOW_REG_sig) begin if reset='1' then DMA_ADDR_LOW_REG_sig <= "00000000"; elsif clock='0' and clock'event then if dma_addr_low_reg_we='1' then DMA_ADDR_LOW_REG_sig <= int_data_bus; else DMA_ADDR_LOW_REG_sig <= DMA_ADDR_LOW_REG_sig; end if; end if; end process; int_data_bus <= DMA_ADDR_HIGH_REG_sig when dma_addr_high_reg_re='1' else DMA_ADDR_LOW_REG_sig when dma_addr_low_reg_re='1' else "ZZZZZZZZ"; c51_dma_addr(10 downto 8) <= DMA_ADDR_HIGH_REG_sig(2 downto 0); c51_dma_addr(7 downto 0) <= DMA_ADDR_LOW_REG_sig(7 downto 0); End DMA_ADDR_REG_a; --******************************************************************************** library IEEE; use IEEE.std_logic_1164.all; library lpm; USE lpm.LPM_COMPONENTS.all; --USE work.LPM_COMPONENTS.all; ---------------------------------------------------------------------- Entity DMA_RAM_ARRAY is port ( clock,reset : in std_logic; int_data_bus : inout std_logic_vector(7 downto 0); c51_dma_access, flash_dma_access, mp3_dma_access : in std_logic; -- for indication DMA user -- MMC mmc_dma_access : in std_logic; -- MMC dma_data_reg_write_flagb : in std_logic; dma_data_reg_we, dma_data_reg_re : in std_logic; -- for C51 SFR access flash_dma_we, flash_dma_re : in std_logic; -- for FLASH controller access -- MMC mmc_dma_we : in std_logic; -- MMC c51_dma_addr : in std_logic_vector(10 downto 0); -- for C51 flash_dma_addr : in std_logic_vector(9 downto 0); --for FLASH controller -- MMC mmc2dma_data : in std_logic_vector(7 downto 0); mmc_dma_addr : in std_logic_vector(9 downto 0); -- MMC flash_data_in : in std_logic_vector(7 downto 0); flash_data_out : out std_logic_vector(7 downto 0); mp3_dma_re : in std_logic; mp3_dma_addr : in std_logic_vector(9 downto 0); mp3_dma_data_out : out std_logic_vector(7 downto 0) -- for TEST -------------------------------- -- DMA_RAM_RE_4TEST : out std_logic; -- DMA_RAM_WE_4TEST : out std_logic; -- DMA_RAM_IN_4TEST : out std_logic_vector(7 downto 0); -- DMA_RAM_OUT_4TEST : out std_logic_vector(7 downto 0); -- DMA_RAM_ADDR_4TEST : out std_logic_vector(3 downto 0) ); end DMA_RAM_ARRAY; architecture DMA_RAM_ARRAY_a of DMA_RAM_ARRAY is signal VCC_H : std_logic; signal DMA_RAM_IN : std_logic_vector(7 downto 0); --signal DMA_RAM_OUT_beforeTRI : std_logic_vector(7 downto 0); signal DMA_RAM_OUT : std_logic_vector(7 downto 0); signal DMA_RAM_ADDR : std_logic_vector(9 downto 0); signal DMA_RAM_WE : std_logic; signal DMA_RAM_RE : std_logic; signal mp3_dma_data_out_sig : std_logic_vector(7 downto 0); begin VCC_H <= '1'; ------------------------------------------------- -- MODELING DMA_RAM_ARRA with LPM_RAM_DQ ------------------------------------------------- u1: lpm_ram_dq GENERIC MAP( LPM_WIDTH => 8, LPM_WIDTHAD => 10, -- 1024 Byte LPM_INDATA => "UNREGISTERED", LPM_ADDRESS_CONTROL => "REGISTERED", LPM_OUTDATA => "REGISTERED" ) PORT MAP( data => DMA_RAM_IN, address => DMA_RAM_ADDR, we => DMA_RAM_WE, q => DMA_RAM_OUT, -- before TRI --inclock => VCC_H, inclock => clock,-- jspark 2001_08_31 outclock => clock ); -- for TEST -------------------------------- -- DMA_RAM_RE_4TEST <= DMA_RAM_RE; -- DMA_RAM_WE_4TEST <= DMA_RAM_WE; -- DMA_RAM_IN_4TEST <= DMA_RAM_IN; -- DMA_RAM_OUT_4TEST <= DMA_RAM_OUT; -- DMA_RAM_ADDR_4TEST <= DMA_RAM_ADDR(3 downto 0); int_data_bus <= DMA_RAM_OUT when DMA_RAM_RE='1' and DMA_RAM_WE='0' and c51_dma_access='1' else "ZZZZZZZZ"; -- flash_data_out <= DMA_RAM_OUT when DMA_RAM_RE='1' and DMA_RAM_WE='0' and flash_dma_access='1' else -- "ZZZZZZZZ"; process(DMA_RAM_OUT,flash_dma_access) begin if flash_dma_access='1' then flash_data_out <= DMA_RAM_OUT; else flash_data_out <= "00000000"; end if; end process; process(reset,clock,DMA_RAM_WE,int_data_bus, c51_dma_access, flash_dma_access,flash_data_in, -- MMC mmc_dma_access, mmc2dma_data) -- MMC begin if reset='1' then DMA_RAM_IN <= "00000000"; elsif clock='1' and clock'event then if c51_dma_access='1' and DMA_RAM_WE='1' then DMA_RAM_IN <= int_data_bus; elsif flash_dma_access='1' and DMA_RAM_WE='1' then DMA_RAM_IN <= flash_data_in; -- MMC elsif mmc_dma_access='1' and DMA_RAM_WE='1' then DMA_RAM_IN <= mmc2dma_data; -- MMC else DMA_RAM_IN <= DMA_RAM_IN; end if; end if; end process; ----------------------------------- -- process(DMA_RAM_OUT, flash_dma_access,flash_dma_re) -- begin -- --if flash_dma_access='1' and flash_dma_re='1' then -- if flash_dma_access='1' then -- flash_data_out <= DMA_RAM_OUT; -- else -- flash_data_out <= "ZZZZZZZZ"; ---- end if; -- end process; process(reset,clock,DMA_RAM_OUT, mp3_dma_access,mp3_dma_re,mp3_dma_data_out_sig) begin if reset='1' then mp3_dma_data_out_sig <= "00000000"; elsif clock='0' and clock'event then if mp3_dma_access='1' and mp3_dma_re='1' then mp3_dma_data_out_sig <= DMA_RAM_OUT; else mp3_dma_data_out_sig <= mp3_dma_data_out_sig; end if; end if; end process; mp3_dma_data_out <= mp3_dma_data_out_sig; --------------------------------------------------------------------------------- -- DMA address / WE,RE control signal selection --------------------------------------------------------------------------------- process(c51_dma_access,flash_dma_access,mp3_dma_access, c51_dma_addr,flash_dma_addr,mp3_dma_addr, -- MMC mmc_dma_access, mmc_dma_addr) -- MMC begin -- if reset='1' then -- DMA_RAM_ADDR <= "0000000000"; -- elsif clock='1' and clock'event then if c51_dma_access='1' then DMA_RAM_ADDR <= c51_dma_addr(9 downto 0); elsif flash_dma_access='1' then DMA_RAM_ADDR <= flash_dma_addr; elsif mp3_dma_access='1' then DMA_RAM_ADDR <= mp3_dma_addr(9 downto 0); -- MMC elsif mmc_dma_access='1' then DMA_RAM_ADDR <= mmc_dma_addr(9 downto 0); -- MMC else DMA_RAM_ADDR <= "0000000000"; end if; -- end if; end process; process(clock,reset,c51_dma_access,flash_dma_access,mp3_dma_access, dma_data_reg_we,dma_data_reg_re, flash_dma_re,flash_dma_we,mp3_dma_re,dma_data_reg_write_flagb, -- MMC mmc_dma_access,mmc_dma_we) -- MMC begin if c51_dma_access ='1' then DMA_RAM_WE <= dma_data_reg_we and not dma_data_reg_write_flagb; DMA_RAM_RE <= dma_data_reg_re and dma_data_reg_write_flagb; elsif flash_dma_access ='1' then DMA_RAM_WE <= flash_dma_we; DMA_RAM_RE <= flash_dma_re; elsif mp3_dma_access ='1' then DMA_RAM_WE <= '0'; DMA_RAM_RE <= mp3_dma_re; -- MMC elsif mmc_dma_access ='1' then DMA_RAM_WE <= mmc_dma_we; DMA_RAM_RE <= '0'; -- MMC else DMA_RAM_WE <= '0'; DMA_RAM_RE <= '0'; end if; end process; ---------------------------------------------------------------------------------- end DMA_RAM_ARRAY_a;