//
// picpram stands for PIC "Program" RAM.
//
// 
// SYNTHETIC PIC 3.0                                          5/1/98
//
//    This is a synthesizable Microchip 16C57 compatible
//    microcontroller.  This core is not intended as a high fidelity model of
//    the PIC, but simply a way to offer a simple processor core to people
//    familiar with the PIC who also have PIC tools.  
//
//    pictest.v  -   top-level testbench (NOT SYNTHESIZABLE)
//    piccpu.v   -   top-level synthesizable module
//    picregs.v  -   register file instantiated under piccpu
//    picalu.v   -   ALU instantiated under piccpu
//    picidec.v  -   Instruction Decoder instantiated under piccpu
//    picdram.v  -   Memory model for the DATA memory (e.g. Register File)
//    picpram.v  -   Memory model for the PROGRAM memory.
//    convert.pl -   Perl script used to translate MPLAB's "Disassembled Code" output
//                   into the Verilog $readmemh compatible file
//    test*.asm  -   (note the wildcard..) Several test programs used
//                   to help debug the verilog.  I used MPLAB and the simulator
//                   to develop these programs and get the expected results.
//                   Then, I ran them on Verilog-XL where they appeared to
//                   match.
//
//    Copyright, Tom Coonan, '97.
//    Use freely, but not for resale as is.  You may use this in your
//    own projects as desired.  Just don't try to sell it as is!
//
//
//
// Synchornous Data RAM, 12x2048
//
// Replace with your actual memory model..
//
module picpram (
   clk,
   address,
   we,
   din,
   dout
);

input		clk;
input [10:0]	address;
input		we;
input [11:0]	din;
output [11:0]	dout;

parameter word_depth = 2048;

reg [10:0]	address_latched;

// Instantiate the memory array itself.
reg [11:0]	mem[0:word_depth-1];

// Latch address
always @(posedge clk)
   address_latched <= address;
   
// READ
assign dout = mem[address_latched];

// WRITE
always @(posedge clk)
   if (we) mem[address] <= din;

endmodule