library ieee;
use ieee.std_logic_1164.all;

entity adder4 is

port (
 signal a,b: in std_logic_vector (3 downto 0);
 signal cin: in std_logic;
 signal sum: out std_logic_vector(3 downto 0);
 signal cout: out std_logic
);


attribute pin_numbers of adder4:entity is 
 "a(3):2 a(2):3  a(1):4  a(0):5 b(3):6 b(2):7  b(1):8  b(0):9 cin:10  " &
  " sum(3):22  sum(2):21  sum(1):20  sum(0):19  cout:18";  

end adder4;

architecture behavior of adder4 is


 signal c: std_logic_vector(4 downto 0);
 begin

    process (a,b,cin,c)
    begin
     c(0) <= cin;
       
     for i in a'range loop

      sum(i) <= a(i) xor b(i) xor c(i);
      c(i+1) <= (a(i) and b(i)) or 
	      (c(i) and (a(i) or b(i)));
     end loop;

     cout <= c(c'HIGH);

 
 end process;

 end behavior;