PPT Slide
architecture a of dpatha is
signal cnta, cntb: std_logic_vector(2 downto 0);
signal en_a: std_logic; -- enable for counter A
signal sum: std_logic_vector(3 downto 0);
signal c1,c2,c3: std_logic; -- carry signals
en_a <= '1' when ((cntb = "110") and (roll = '1')) else '0';
stateff: process (clk,reset)
cnta <= "001"; -- initialize both counters to '1'
elsif (clk'event and clk='1') then
when "001" => cntb <= "010";
when "010" => cntb <= "011";
when "011" => cntb <= "100";
when "100" => cntb <= "101";
when "101" => cntb <= "110";
when "110" => cntb <= "001";
when others => cntb <= "001";
when "001" => cnta <= "010";
when "010" => cnta <= "011";
when "011" => cnta <= "100";
when "100" => cnta <= "101";
when "101" => cnta <= "110";
when "110" => cnta <= "001";
when others => cnta <= "001";